登录
首页 » VHDL » 频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分...

频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分...

于 2022-01-25 发布 文件大小:88.05 kB
0 142
下载积分: 2 下载次数: 1

代码说明:

频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz); 当输入信号的频率大于相应量程时,有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measurement range of 1MHz, the measured value through the four LED 8421BCD code shows the form of output can be controlled through the switch range, range at 10kHz, 100kHz, 1MHz Three (maximum reading were 9.999kHz, 99.99kHz, 999.9kHz) when the input signal is greater than the corresponding frequency range, it shows overflow.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • liushuxian
    中文版DLX流水线技术相关方面介绍以及简单应用 适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application Suitable for beginners to explain face)
    2014-12-09 21:33:45下载
    积分:1
  • M_SSB_100
    由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
    2007-07-25 14:59:29下载
    积分:1
  • 电子闹钟:基于fpga的电子闹钟设计,采用模块化方式
    电子闹钟:基于fpga的电子闹钟设计,采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
    2022-02-06 03:24:59下载
    积分:1
  • VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料
    VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料-VHDL hardware description language and digital logic circuit design, VHDL learning good information
    2022-11-11 07:30:07下载
    积分:1
  • GAL16V8(fangzhen74LS138)
    GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时,对简化走线特别有用。简单的修改GAL16V8程序,可灵活地进行地址译码修改。(GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modifications GAL16V8 program, the flexibility to change the address decoding.)
    2011-01-26 20:43:01下载
    积分:1
  • exercise3
    用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
    2013-08-30 11:12:09下载
    积分:1
  • uart_slip
    实现串口通讯以及SLIP协议传输数据,增加了特殊字符的转义(Realization of Serial Communication and SLIP Protocol)
    2021-01-19 18:58:41下载
    积分:1
  • 21452547
    加减可控制的十到十六进制计数器。完全准确,可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)
    2016-01-11 12:46:04下载
    积分:1
  • recarry
    fir filter 程序 老师上课留的作业,在这里跟大家分享一下,希望能有所帮助(fir filter procedures teacher in the class to stay the operation here to share with you, hope can be helped)
    2006-10-11 19:34:43下载
    积分:1
  • FPGA-powe-analysis-tool-EPE
    FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)
    2012-11-19 17:08:00下载
    积分:1
  • 696518资源总数
  • 106215会员总数
  • 5今日下载