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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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This is an FPGA
这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
- 2022-02-02 20:49:24下载
- 积分：1
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switch--circuit
最近交互式电源技术，软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)
- 2013-11-25 15:56:17下载
- 积分：1
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基于sopc ep2c5开发板的rs232例程
基于sopc ep2c5开发板的rs232例程-On sopc ep2c5 development board rs232 routines
- 2022-02-05 03:28:05下载
- 积分：1
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xilinx 开发板程序，VGA控制显示
xilinx 开发板程序，VGA控制显示-Xilinx development board procedures, VGA display control
- 2022-03-29 02:35:53下载
- 积分：1
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vendingmachine
vendingmachine vhdl code
- 2011-12-03 20:53:39下载
- 积分：1
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Verilog_traffic
若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)
- 2020-07-17 21:08:48下载
- 积分：1
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sdram_module3
能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分：1
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vhdl,序列信号发生器，发出11101010，可更改为任意序列
vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
- 2023-08-12 03:05:03下载
- 积分：1
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PSK
实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)
- 2013-04-10 14:24:53下载
- 积分：1
