-
Poiseuille---BANFANTAN
格子玻尔兹曼方法模拟poiseuille流,半反弹边界,适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)
- 2021-04-07 13:29:01下载
- 积分:1
-
DE2_CCD
说明: 此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)
- 2011-04-17 09:43:37下载
- 积分:1
-
LCD_1602
说明: 以ISE为开发环境,Verilog语言编写程序。功能:FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分:1
-
liyuanlnx_dynamic_led
FPGA数码管显示秒表实验
三种方法实现:
方法一: 对秒计数,得到(秒显示)0~9,
对(秒显示)计数,得到(分秒显示)0~5,
对(分秒显示)计数,得到(分钟显示)0~5,
注意进位时机
方法二: 对秒计数,得到(秒显示)0~9
对秒计数,得到(分秒显示)0~5
对秒计数,得到(分钟显示)0~5
方法三:
只对秒计数,分别取模
%60得到分钟显示 ************************
余数%10得到分秒显示 (据说)取模运算占资源!!!!(也能接受?好像...)
再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA
Three ways to achieve)
- 2020-06-22 04:40:02下载
- 积分:1
-
100powertips
these are the source codes for the book " 100 power tips for FPGA designers"
- 2012-08-20 14:59:29下载
- 积分:1
-
FPGA
基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)
- 2010-10-12 21:34:00下载
- 积分:1
-
8BIT_CPU
一个8位的CPU设计,用verilog语言写的,希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分:1
-
SDRAM_DDR
SDRAM_DDR控制器verilog代码及中文说明文档。(The SDRAM_DDR controller Verilog code and documentation in chinese.)
- 2013-02-06 10:48:57下载
- 积分:1
-
层合板刚度
层合板的刚度的计算和验算,包括拉伸刚度A、弯曲刚度D以及耦合刚度B。
首先要给定层合板的各个参数,具体有:层合板的层数N;各单层的弹性常数E1、E2、 、G12;各单层对应的厚度;各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)
- 2021-01-18 09:28:43下载
- 积分:1
-
高级加密标准AES的FPGA实现,支持128,256密钥长度格式
高级加密标准AES的FPGA实现,支持128,256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
- 2022-03-25 02:47:08下载
- 积分:1