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AD9361
说明： AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)
- 2021-01-07 14:38:53下载
- 积分：1
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fpga clock design, the information is better, for your reference, non
fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh
- 2022-10-20 15:50:02下载
- 积分：1
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四通道DDS信号发生器
四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
- 2021-03-08 14:49:28下载
- 积分：1
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RISC
URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分：1
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SD_Controller_Verilog
说明： 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。(This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.)
- 2021-04-05 17:39:03下载
- 积分：1
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BCH_EncDec_Matlab
bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分：1
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vhdl code for counterand detemines how counter
works
vhdl code for counterand detemines how counter
works
- 2023-03-20 20:40:03下载
- 积分：1
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SinGen
使用Verilog编写的正弦波生成工程，使用ROM核产生，利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)
- 2015-04-24 16:40:21下载
- 积分：1
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am
说明： 基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)
- 2013-10-14 22:14:56下载
- 积分：1
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edc_spi_command
单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分：1
