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数字信号处理的FPGA实现(第4版)源码
数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
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verilog
VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子(Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of)
- 2008-05-28 22:12:57下载
- 积分：1
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61EDA_D888
基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)
- 2010-01-07 18:30:10下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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01-USB
usb读取，仅供参考，在实际应用中要更改以下数据。(Read usb data)
- 2012-12-24 15:35:40下载
- 积分：1
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Verilog-detail
不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)
- 2013-03-26 13:01:23下载
- 积分：1
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用verilog实现UART协议
UART包括发射机和接收机。发送器本质上是一个加载数据的特殊移位寄存器；
- 2022-04-09 00:02:07下载
- 积分：1
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crc_verilog_xilinx
crc校验，非常好用，是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)
- 2021-03-01 11:49:34下载
- 积分：1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分：1
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test_utils.tar
GPIO LED 测试工具源代码，可以用来检测开发的主板GPIO LED设备是否工作正常(GPIO LED test tool source code, can be used to detect the development of motherboard GPIO LED device is working properly)
- 2012-10-23 10:20:56下载
- 积分：1
