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代码说明：

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

文件列表：

csdn, 0 , 2021-01-15
csdn\ALU.v, 312 , 2021-01-15
csdn\CLA_32.v, 618 , 2021-01-15
csdn\CLA_4.v, 1797 , 2021-01-15
csdn\CONUNIT.v, 1371 , 2021-01-15
csdn\DATAMEM.v, 278 , 2021-01-15
csdn\EXT16T32.v, 225 , 2021-01-15
csdn\INSTMEM.v, 1500 , 2021-01-15
csdn\MUX2X32.v, 228 , 2021-01-15
csdn\MUX2X5.v, 223 , 2021-01-15
csdn\MUX4X32.v, 338 , 2021-01-15
csdn\PC.v, 456 , 2021-01-15
csdn\PCadd4.v, 148 , 2021-01-15
csdn\REGFILE.v, 1503 , 2021-01-15
csdn\SHIFTER32_L2.v, 117 , 2021-01-15
csdn\SHIFTER_COMBINATION.v, 167 , 2021-01-15
csdn\TEST.v, 217 , 2021-01-15
csdn\mips.v, 1020 , 2021-01-15