88E1116R_Datasheet
88E1116R_Datasheet，marvell以太网phy芯片手册，全本88E1116RM A RV E LL. Alaska Gigabit Ethernet TransceiverOVERVIEWFEATURESThe Alaska 88E1116R Gigabit Ethernet Transceiver is10/100/1000BASE-TIEEE 802.3 complianta physical layer device containing a single GigabitSupports reduced pin count GMII(RGMID)interfaceEthernet transceiver. The transceiver implements theFour RGMii timing modesEthernet physical layer portion of the 1000BASE-T,100BASE-TX. and 10base-t standards. t is manufacIntegrated mdi interface termination resistors thateliminate twelve passive componentstured using standard digital CMOS process and con-tains all the active circuitry required to implement theEnergy Detect and Energy Detect+ low powerphysical layer functions to transmit and receive data onmodesstandard Cat 5 unshielded twisted pairThree loopback modes for diagnosticsThe 88E1116R device has two regulators to generateDownshift"mode for two-pair cable installationsall required voltages. The 88E1116R device can beFully integrated digital adaptive equalizers, echopowered by a single 1.8V, 2.5V, or 3. 3V supply Alternacancellers, and crosstalk cancellerstively, if the regulators are not used, then the 88E1116RAdvanced digital baseline wander correctiondevice can be powered by a 1. 8v and 1.2V supplyAutomatic MDi/MDIX crossover at all speeds ofThe 88E1116R device incorporates the Marvell@ VirtualoperationCable Tester (VCTTM)feature, which uses TimeAutomatic polarity correctionDomain Reflectometry(TDR)technology for the remotelEEE 802. 3u compliant Auto-Negotiationidentification of potential cable malfunctions, thusSoftware programmable LEd modes including LEDreducing equipment returns and service calls. UsingtestingVCT, the alaska 88E1116R device detects and reportspotential cabling issues such as pair swaps, pair polar-Supports IEEE 1149.1 JTAGity and excessive pair skew. The device will also detectMDC/MDIO Management Interfacecable opens, shorts or any impedance mismatch in theCRC checker, packet countercable and reporting accurately within one meter the disPacket generationtance to the faultVirtual Cable Tester(VCT)The 88E1116R device integrates MDI interface terminaAuto-Calibration for MAc Interface outputstion resistors into the Phy. this resistor integrationComa Mode supportfacilitates board layout and reduces board cost byRequires a single 1.8v supplyreducing the number of extenal components. The new10 pads can be supplied with 1.8V, 2.5V, or 3. 3VMarvell calibrated resistor scheme will achieve andexceed the accuracy requirements of the IEEE 802.3Two regulators generate all required voltagesRegulator can be supplied with 1.8V,2.5V or 3.3Vreturn loss specificationsCommercial gradeThe 88E1116R device supports the reduced gmll64-Pin QFN package(RGMI)for direct connection to a MAC/Switch portThe 88E1116R device uses advanced mixed-signal processing to perform equalization, echo and crosstalkcancellation, data recovery, and error correction at agigabit per second data rate. The device achievesrobust performance in noisy environments with very lowpower dissipationThe 88E 1116R device is offered in a 64-pin QFn pack-The 88E1116R device is footprint compatible with the88E1116 device As the 88E 1116R device employs integrated MDi interface terminations, all external mDIinterface termination resistors and capacitors must beremoved when migrating from the 88E1116 to88E1116R. See 88E1116 to 88E1116R Migration Appli-cation note for more detailsCopyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 388E1116RMARVELLo Alaska Gigabit Ethernet TransceiverMagnMedia Types10/1001000Mbps88E1116R|a盖10BASEEthernet macRJ-45Device100BASE-TX1000BASE-TMAC InterfaceRGMII88E1116R Device used in Copper ApplicationDoc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 4Document Classification: Proprietary InformationMarch 1. 2007. AdvanceTable of contentsSECTION 1. SIGNAL DESCRIPTION1.1 Pin Description101.1.1 Pin Type Definitions1264 Pin QFN Pin Assignment List- Alphabetical by Signal Name.……,…,,…,161.3 O State at Various Test or reset modes .mmm.,17SECtION 2. FUNCTIONAL SPECIFICATIONS2.1 Copper Media Interface..国面画192.2 MAC Interface(RGMII)4192.2.1 10/100 Mbps Functionality2.2.2 TX ER and RX ER Codingaaaaaiiaia t23Lo。 pback……………,….….….,.,…….…,…,….….……,…….……………212.3.1 MAC Interface Loopback212.3.2 Line Loopback.222.3.3 EXternal Loopback24 Synchronizing F|FQ….…,,…,…,,,,,,…,,,,,…,,,…,,,,…,……242.5 Copper Media Transmit and receive Function.man..m日a252.5.1 Transmit side Network Interface252.5.2 Encoder2.5.3 Receive Side Network Interface2.5. 4 Decoder2.6 Regulators and Power Supplies282.6.1 AVDD2.6.2 AVDDC282.6.3 AVDDR292.6.4 AVDDX2.6.5DVDD…292.6.6 VDDO26.7 VDDOR.292.7 Power Management302.7.1 Low Power Modes2.72 Low Power Operating Modes……2.7.3 RGMl Effect on Low Power modes3228Auto- Negotiation.........……33Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 588E1116RMARVELL Alaska Gigabit Ethernet Transceiver2.9 Downshift Feature…352.10 Advanced virtual Cable Tester362.10.1 Maximum Pe2.10.2 First Peak372.10.3 Offsetp2. 10. 4 Sample Poin2.10.5 Pulse Amplitude and Pulse Width392. 10.6 Drop Link...392.10.7 VCTTM With Link Up392.11 Data Terminal Equipment (DTE)Detect........2.12 CRC Error Counter and frame Counter412.12. 1 Enabling the crc error counter and frame counter.412.13 Packet generator412.14 MDI/MDIX Crossover422.15P。 olarity Correction..…432.16LED,,,,,,,,,,,…,…,,442.16.1 LED Polarity452.16.2 Pulse Stretching and Blinking.462. 16.3 Bi-Color LED Mixing472.16.4 Modes of Operation482.17 EEE 1149.1 Controller522.17.1 BYPASS Instruction522.17.2 SAMPLE/PRELOAD Instruction.52217.3 EXTEST Instruction552,17.4 The clamP Instruction552,17.5 The high-z Instruction552.17.6 ID CODE Instruction552.18 Interrupt.552.19 Automatic and Manual Impedance Calibration.……,…,…,…,…,…,…,……562. 19. MAC Interface calibration circuit562.19.2 MAC Interface Calibration Register Definitions2. 19.3 Changing Auto Calibration Targets2. 19. 4 Manual Settings to The Calibration Registers“““582.20 Configuring the 88E1116R Device..2.20. 1 Hardware Configuration612.20.2 Software Configuration-Management Interface632.21 Temperature sensor64Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellDocument Classification: Proprietary InformationMarch 1. 2007. AdvanceSECTION 3 REGISTER DESCRIPTION65SECTION 4, ELECTRICAL SPECIFICATIONS1104.1. Absolute Maximum Ratings,…,…,…,…,,…,…,…,…,…,…,,…,…,……,1104.2. Recommended Operating Conditions..,,.,……,,……1114.3. Package Thermal Information.………….……….…………1124.3.1 Thermal Conditions for 64-pin QFn Package1124. 4. Current Consumption...........面量量…1134.4.1 Current Consumption AVDD..1134.4.2 Current Consumption AVDDC..1134.4.3 Current Consumption AVDDR1144.4.4 Current Consumption AVDDX1144.4.5 Current Consumption DVDD4.4.6 Current Consumption VDDo1154.4.7 Current Consumption VDDOR1154.4.8 Current Consumption Center Tap1154.5. DC Operating Conditions1164.5.1 Non-RGMlI Digital Pins1164.5.2 Internal resistor Description4.5.3 Stub-Series Transceiver LogIc (55/.21174.5 4 EEE DC Transceiver Parameters1194.6. AC Electrical Specifications1204.6.1 Reset Timing ..1204.6.2 XTAL IN/XTAL OUT Timing1214.6.3 LED to CONFIG Timing1214.7 RGMII Interface Timing……,,…1224.7.1 RGMl AC Characteristics4.7.2 RGMII Delay Timing for different RGMiI Modes1234.8. MDC/MDIO Timing…12549. JTAG Timing…,,…1264.10.EEE AC Transceiver parameters1274.11. Latency Timing........….…1284.11.1 RGMII to 1000BASE-T Transmit Latency Timingaa“aa1284.11.2 RGMII to 100BASE-TX Transmit Latency Timing1284.11.3 RGMiI to 10BASE-T Transmit Latency Timing4. 11. 4 1000BASE-T to RGMll Receive Latency Timing1304. 11.5 100BASE-TX to RGMII Receive Latency Timing.1304.11.610 BASE-T to RGMll Receive Latency Timing……….….…………,130SECTION 5. PACKAGE MECHANICAL DIMENSIONS1315.1 64-Pin QFN Package...131Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 788E1116RMARVELL Alaska Gigabit Ethernet TransceiverSECTION 6. ORDER INFORMATION1336.1 Ordering Part Numbers and Package Markings1336.1.1 RoHS 5/6 Marking Example1346.1.2 RoHS 6/6 Marking Example135Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 8Document Classification: Proprietary InformationMarch 1. 2007. AdvanceSignal DescriptionSection 1. Signal DescriptionThe 88E1116R device is a 10/100/1000BASE-T Gigabit Ethernet transceiverFigure 1: 88E1116R Device 64-Pin QFN Package(Top view)文gg9廿廿廿廿廿廿凵廿廿廿凵廿守令导好寸守哥导$85#將RX CTRL4932TSTPTRXDIO5031MDIPIORXD[51EPAD-VSS30d MDIN[O]VDDOR52290 AVDDRX CLK5328叫NCRXD[2]54AVDDRXD]5526MD|P[1VDDOR56VREF57MARVEL L③24E MDIP[2TXD0]□5823MDIN[2TXD[1]B5988E1116R22AVDDTX_CLK F6021AVDDTXD[2Top ViewMDIP[3TXD3]□62190 MDIN[3]TⅩCTRL6318□NCCONFIG[O]64CTRL18三s回口cc×O百口口艺艺安安Copyright o 2007 MarvellCONFIDENTIALDoc. No. MV-S104224-00 RevMarch1.2007. AdvanceDocument Classification: Proprietary InformationPage 988E1116RMARVELL. Alaska Gigabit Ethernet Transceiver1.1 Pin Description1.1.1 Pin Type DefinitionsPin Ty peDefinitionHInput with hysteresisVOInput and outputInput onlOutput onlPUIntemal pullPDInternal pull downOpen drain outputTri-state outputADC sink capabilityDoC. No. MV-S104224-00 RevCONFIDENTIALCopyright o 2007 MarvellPage 10Document Classification: Proprietary InformationMarch.2007. Advance
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上海大学计算机组成原理历年试卷
上海大学计算机组成原理历年试卷，文档形式，内部资料。[X]补=0010011Y]补=00.11001:[-Y]补=10011(7分,过程4分,结果3分)被除数商说明0010011000000被除数与除数同号+1100111+[Y]补I1101000000*0余数语除数异号,商上011101000000*00左移1位011001上次商0,+Y]补011010000*01余数与除数同号,商10011010000*010左移1位+1100111上次商1,+Y]补0000001000*011余数与除数同号,商1000001000*0110左移1位+11001上次商1,十[-Y]补110100100*010余数与除数异号,商0+0010010上次商0,+Y]补11010110*01100余数与除数异号,商01010110冰011000左移1位011001商末位置1结果:0.110012、已知替换算法LRU当前的信息块在登记表中的排序为0、1、2、3、4、5,画图依次表示出在先后使用3、1、4时登记表中信息块排序的变化过程(0)(组分别是3、3、4分)原始使用3使用1使用440原则:把最近使用的资快提到最前面,替换最下面的3、已知内存地址为0~1M单元 Cache地址为01k单元,设每块为256个单元,设计一组组相连 Cache组织。(1)给出数学描述和说明(10)(2)出简图(图中的 Cache块和内存块应标明具体地址)(10描述(10分)具体分两组组相连映像方式是以组为单位,组与组间是直接映像组内是全相连映像例如, cache为4块将 cache分为两组每组512字节,分为两块此时取k=0,1则第j块内存地址映射为j=(i mod 2)*2+kk=0, 1图10分第1页(共6页)上海大学2003~2004学年秋季学期试卷(A卷)课程名:计算机组成原理学分:4(闭卷学号:姓名:院、系:成绩题号四五六七得分得、填空:(每格2分,共20分)l、存储器总体上按照存储介质分为2、存储器接到读/写命令到完成读/写操作所需要时间称为。存储器进行两次连续读/写操作所需要的最小间隔时间称为3、半导体动态RAM靠存储信息。4、直接由计算机硬件执行的程序是5、组成一个32K×8的存储器当分别选用1K×4位、16K×1位、2K×8位的三种不同规格的存储芯片时,各需片。得分、简答题(每题5分,共35分)1、画图并说明32位浮点数的规格化表示,并举例说明其精度及数据范围2、只读存储器分为那几类,各自的功能3、画图表小静态存储器地址信号首先选通时Adr、CS、Dout的开关特性信号次序)。并简述为什么试卷纸第2页(共6页)4、简述为保持 Cache和主存一致性而定义的 Cache的两种写入方式5、简述动态存储器刷新的两种工作方式6、简述段式和页式虚拟存储器的特点7、读写存储器的分类,各自的特点得分三、综合题(45)设X=0.10011,Y=0.11001写出一种两位定点乘法和一种位定点除法的计算过程并给出计算结果(15)FCLLUFLT.TV-了k平小T一廿性XJ试卷纸第3页(共6页)2、已知替换算法LRU当前的信息块在登记表中的排序为0、1、2、3、4、5,画图依次表示出在先后使用3、1、4时登记表中信息块排序的变化过程(10)。命题纸使用说明:1、字迹必须端正,以黑色碳素墨水书写在框线内,文字与试卷纸第4页(共6页)3、已知内存地址为0-M单元, Cache地址为0~1k单元设每块为256个单元,设计一组组相连 Cache组织。(1)给出数学描述和说明(10)(2)画出简图(图中的 Cache块和内存块应标明具体地址)(10)命题纸使用说明:1、字迹必须端正,以黑色碳素墨水书写在框线內,文字与草稿纸第5页(共6页命题纸使用说明:1、字迹必须端正,以黑色碳素墨水书写在框线内,文字与草稿纸第6页(共6贝丿
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