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C++实现的单纯形算法计算程序
C++实现的单纯形法计算程序，输入变量规模自动生成问题然后解出来
- 2020-12-10下载
- 积分：1
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全志 F1C600完整手册
The F1C600 processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of boombox markets. F1C600 processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C600 supports Full HD video playback, iAllwinnerTechnologyRevision HistoryRevision historyVersionateDescriptionV1.0NoV10,2015nitia|Re|ease∨ersⅰonF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 3AllwinnerTechnologyRevision HistoryTable of contentsDeclaration2Revision histeD。着,着垂Table of contents.:::::.:::::1:4Chapter 1.About This Documentation361.1 Documentation overview36Chapter 2 Overview....372.1 Processor features2.1.1, CPU Architecture2.2. Memory Subsystem....................382.2.1. Boot rom382.2.2 SDRAM382.2.3. SD/MMC Interface..:::··:·.:::::..:·.:::::::::::··:382.3. System Peripheral.382.3.1. Timer.382.3.2.|NT392.3.3.CCU392.3.4.DMA,392.3.5.PWM,392.4. Display subsystem39241. Display engine…,,…...:::::392.4.2. Display output.....39F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 4AllwinnerTechnologyRevision History2.5. Video Engine26.| mage Subsystem…D看看1,翻看、·着国,着,,,面面,2.6.1.CS|4看402.6. 2 CVBS Input402. 7. Audio Subsystem2.7.1, Audio codec2.8. System Peripherals2.8.1.USB2.00TG412.8.2. KEYADC412.8.3.Tl:::::412.8.4. Digital Audio Interface.....................2.8.5.UART412.8.6.SP412.8.7.TW|422.8.8.CIR422.8.9,RSB422.8.10.OWA.422.9 Package422.10. System block Diagram43Chapter3. System..........................,443.1. Memory Mapping….453.2. CCU2463.21 Overy3.2.2, FeatureF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 5AllwinnerTechnologyRevision History3.2.3. Functionalities Description3.23.1. System bus….:.:::..a...:::::::非3.23.2 Bus clock tree473.2.4. CCU Register List…….473.2.5. CCU Register Description483.2.5. 1 PLL CPU Control Register3.2.5.2. PLL AUDIO Control register......................493.2.5.3. PLL VIDEO Control Register503.2.5.4. PLL VE Control Register513.2.5.5. PLL DDR Control Register3.2.5.6. PLL PERIPH Control Register...............523.2.5.7. CPU Clock Source register533.2.5.8. AHB/APB/HCLKC Configuration Register543.2.5.9. Bus Clock Gating Register O.......553.2.5. 10. Bus Clock Gating Register 1................553. 2.5.11. Bus Clock Gating Register 2563.2.5.12. SDMMCO Clock Register583.2.5.13. SDMMCl Clock Register.58325.14. DAUDIO Clock Register……593.2.5.15. OWA Clock Register.........................593.2.5.16. CIR Clock Register.603.2.5.17. USBPHY Clock Register603.2.5. 18 DRAM Gating register.603.2.5. 19 BE Clock Register61F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 6AllwinnerTechnologyRevision History3.2.5.20. FE Clock Register623. 2.5.21. TCON Clock Register623.2.5.22. De-interlacer Clock Register623.2.5.23. TVE Clock Register∴633.25.24. TVD Clock Register……643.2.5.25. CSI Clock Register643.2.5.26. VE Clock Register.......653.2.5.27. AUDIO CODEC Clock Register653.2.5.28. AVS Clock Register.653.2.5.29. PLL Stable Time register 0653.2.5.30. PLL Stable Time Register 1...............................................................653.2.5.31. PLL CPU Bias register663.2.5.32. PLL AUDIO Bias Register663.2.5.33. PLL VIDEO Bias Register663.2.5. 34 PLL VE Bias Register673.2.5.35.PLL_ DDR Bias Register…..,…,…,…673.2.5.36.PLL_PER| PH Bias Register……673.2.537.PLL_ CPU Tuning Register.……683.2.5.38. PLL DDR Tuning Register683.2.5.39. PLL AUDIO Pattern Control register........................693.2.5.40. PLL VIDEO Pattern Control Register.693.2.5. 41. PLL DDR Pattern Control Register3.2.5.42. Bus Software Reset Register O..3.2.5.43. Bus Software Reset register 1F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 7AllwinnerTechnologyRevision History3.2.5.44. Bus Software Reset Register 23.2.6. Programming guidelines3.2.6.1.PLL4看3.2.6.2.BUS3.3. Timer743.3 1. Overvi翻着看743.3.2, Feature…743.3.3. Functionalities Description..743.3.3.1. Typical Applications743.3.3.2. Functional block Diagram753.3.4.Timer Register List.......................753.3.5. Timer Register Description3.3.5.1. Timer IRQ Enable Register...763.3.5.2. Timer iRQ Status Register3.3.5.3. Timer 0 Control Register3.3.5.4. Timer o Interval value register .................................3.3.5.5. Timer 0 Current Value Register3.3.5.6. Timer 1 Control Register....3.3.5.7. Timer 1 Interval value register,7933.58. Timer1 Current Value Register…....…793.3.5.9. T imer 2 Control register3.3.5.10. Timer 2 Interval value Register803.3.5. 11 Timer 2 Current Value register3.3.5. 12 AVS Counter Control Register81F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 8AllwinnerTechnologyRevision History3.3.5.13. AVS Counter O Register.81335.14. AyS Counter1 Register.,,…,;…,…,…,…813.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…3.3.5.16. Watchdog irQ Enable Register.………823.3.5.17. Watchdog statusster823.3.5.18. Watchdog Control Register83335.19. Watchdog Configuration Register……,,,…833.3.5.20. Watchdog Mode register....833.3.6. Programming Guidelines843.3.6.1. Timer,,84336.2. Watchdog….…843. 4, PWM853.4.1. Overview853.4.2 Feature853.4.3. Functionalities Description853. 1. Functional Block Diagram......着,着面853.4.4. Operation Principle863. 4.4.1. PWM output pins863.4.5. PWM Register List……3.4.6. PWM Register Description.....................3.4.6.1. PWM Control Register.3.4.6.2. PWM Channel 0 Period Register883.4.6.3. PWM Channel 1 Period register893.5.NTC.90F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 9AllwinnerTechnologyRevision History3.5.1. Overview903.5.2, Feature.:..:.:::::a:::.:::.:.a..:::::.:::::903.5.3. Functionalities Description903.5.3.1. Functional Block Diagram903.5.4.Interrupt source913.5.5. INTC Register List.....................................3.5.6. INTC Register Description…923.5.6.1. Interrupt Vector Register.……923.5.6.2. Interrupt base Address register933.5.6.3. NMI Interrupt Control Register933.5.6.4. Interrupt irQ Pending register o933.5.6.5. Interrupt iRQ Pending register 1...............933.5.6.6. Interrupt Enable register o933.5.6.7. Interrupt Enable Register 1.............933.5.6.8. Interrupt Mask register 0943.5.6.9. Interrupt Mask Register 1.::::943.5.6.10. Interrupt Response Register O.......943.5.6.11. Interrupt Response Register 1943.5.6.12. Interrupt Fast Forcing register 0943.5.6.13. Interrupt Fast Forcing Register 1....................................................................953.5.6. 14 Interrupt Source Priority Register O953.5.6.15. Interrupt Source Priority Register 1...973.5.6.16. Interrupt Source priority register 21003.5.6. 17 Interrupt source priority register 3102F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 10
- 2020-11-28下载
- 积分：1
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pso算法优化pid控制参数
用粒子群pso算法优化pid控制的参数，matlab源代码，非常实用！
- 2020-12-12下载
- 积分：1
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基于MATLAB语音信号采集与分析的毕业论文设计
基于MATLAB语音信号采集与分析的毕业论文设计程序论文都有
- 2020-12-03下载
- 积分：1
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Altium贴片电感封装库3D库、铝电解电容封装库
AD贴片电感，铝电解电容封装库，贴片功率电感的PCB封装。
- 2020-12-05下载
- 积分：1
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光纤通信中数字信号处理
论文，高速光纤通信与数字信号处理。相干光接收，频偏估计，相位估计，算法。Y175785独创性(或创新性)声明本人声明所呈交的论文是本人在导师指导下进行的研究工作及取得的研究成果。尽我所知,除了文中特别加以标注和致谢中所罗列的内容以外,论文中不包含其他人已经发表或撰写过的研究成果,也不包含为获得北京邮电大学或其他教育机构的学位或证书而使用过的材料。与我一同工作的同志对本研究所做的任何贡献均已在论文中作了明确的说明并表示了谢意。申请学位论文与套料若有不实之处,本人承担一切相关责任。本人签名:-/b日期:200列2关于论文使用授权的说明学位论文作者完全了解北京邮电大学有关保留和使用学位论文的规定,即:研究生在校攻读学位期间论文工作的知认产权单位属北京邮电大学学校有权保留并向国家有关部门或机构送交论文的复印件和磁盘,允许学位论文被查阅和借阅:学校可以公布学位论文的全部或部分内容,可以允许采用影印、缩印或其它复制手段保存、汇编学位论文。本人签名:日期:20°3.2导师签名:日期:100Gb/ s PM-QPSK相干光接收机载波频偏估计和相位恢复算法的研究摘要通信网络中高速率业务的不断发展,对现有的城域网络及省际、国际骨干通信网络的传输带宽提出了更高、更迫切的要求。从目前主流的1040Gbp光传输技术向100Gbs演进成为光传输技术的发展趋势。近年来大量研究表明,相位调制及相干接收是最具前景的100Gbs光传输方式。其中,采用相干接收技术的偏振复用QPSK( PM-QPSK传输系统最被业界认可。该系统的符号速率比比特率降低4倍,因此有较高的光谱利用率,且收发机结构相对简单实现相对容易。此外,信道中的各种损伤,如色散、载波频偏、相位偏移等导致的信号损伤,都能在接收机中通过电域的数字信号处理(DSP)来灵活地补偿。对调相信号,载波与本振间的频率和相位偏移会使信号产生较大的相位失真,频偏估计和相位恢复成为相干接收机中两个重要的功能模块。本文在国家863计划课题“1000b/s相干光传输关键技术研究(2009AA01Z221)”资助下,对上述系统接收机载波频偏和相位恢复算法展开了深入研究,主要内容如下:1.研究了 PM-QPSK的系统组成结构,重点研究了接收机DSP各组成模块的功能,并设计实现了相干接收机后端Maab仿真平台。2.详细分析了载波频偏估计算法,设计了算法并行处理实施方案以解决现有硬件处理速率不足够高的问题,并仿真验证了方案的可行性。设计了四次方频偏估计算法的并行结构;提出了基于误码性能反馈的 BA-PADE( BER-Aided pre-decision- based Angle DifferentialEstimator)算法,解决了传统PADE要求初始频偏设置与真实频偏接近的问题;提出了基于PADE的并行处理算法一一分组PADE( Grouped-PADE)。所设计方案均通过系统仿真验证了可行性。3.详细分析了载波相位恢复算法,为采用现有FPGA或DSP实现l00Gb/级信号处理,设计了载波相位恢复并行处理方案并仿真验证了方案的可行性。设计了基于Ⅴ iterbj- Viterbi的优化算法及其并行处理结构,将其同频偏估计并行算法联合进行了二进制定点仿真分析,仿真结果表明并行处理方案可显著降低硬件处理速率要求。关键词光传输相干接收频偏相位恢复THE RESEARCH OF FREQUENCY OFFSET ESTIMATIONAND PHASE RECOVERY ALGORITHMFOR 100Gbs OPTICAL COHERENT PM-QPSK RECEIVERABStRcTThe rapid development of high bit-rate services in communicationnetworks has instantly demanded a much higher bandwidth of coretransmission links in WAN, inter-province and international networks.The upgrade from the existing 10G/40G optical transmission to 100G hasbeen a trend. The research in recent years indicates that systems withphase modulation and coherent detection are the most promising, ofwhich PM-QPsk gets most recognitionThe PM-QPsK lowers the symbol rate as 1/4 of bit rate whichprovide high spectrum efficiency, and the transceiver structure ofPM-QPSK is simpler and so is easier to realize. Besides, with digitalalgorithms, the electrical Digital Signal Processing(DSP)in thee receivercan flexibly compensate the channel distortion caused by dispersion,carrier frequency offset and phase distortion. Since the phase distortioncaused by frequency and phase offset between lo and carrier is one ofthe main distortions in PM-QPSK, frequency offset compensation andphase recovery act as two of the core modules.With the support of National 863 Project"Research of the KeyTechnologies of 100Gb/s Optical Coherent Transmission Systems?", thisthesis mainly focuses on the research of the digital algorithms of carrierfrequency offset compensation and carrier phase recovery in the receiverof PM-QPSK system and the main contents are as follows1. Investigation of PM-QPSK structure, mainly on the receiver DSPstructure, including function of the several modules in this partDesigning and implementation of the Matlab simulation platform for theback-end of PM-QpsK receiver.2. Analysis on the carrier frequency offset estimation algorithmsdesigning of the parallel structure of the algorithms in order to break therestriction of hardware speed, with feasibility testified by simulationDesigning of the parallel structure of the 4 power method Designing ofBA-PADE (BER-Aided Pre-decision-based Angle Differential Estimator)based on BER feed-back to break the exact initialization restriction oftraditional PADE. Designing of a parallel operation scheme based onPADE, namely Grouped-PADE. Feasibility of both the forementionedscheme testified by simulation.3. Analysis on the carrier phase recovery algorithms, designing ofthe parallel operation scheme in order to realize phase recovery in100Gb/s PM-QPSK with current FPGA or DSP, with feasibility testifiedby simulation. Designing of the optimized and the parallel structure ofViterbi- Viterbi (V-V)method, and binary fixed-point simulation ofparallel v-v together with frequency offset algorithm, the result provedthat the scheme could observably lower the request to the hardwareoperation speedKEYWORDS optical transmission coherent detectionfrequency offset phase recovery
- 2020-12-05下载
- 积分：1
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NRF24L01图片传输
用STM32作为处理器，NRF24L01作为传输手段来传输图片或者视频
- 2021-05-06下载
- 积分：1
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A星算法的matlab实现，官方版本
这是matlab官方的Astar算法的实现，代码比较规整，值得学习。标准的Astar实现
- 2020-06-29下载
- 积分：1
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BP神经网络法确定工程材料评价指标的权重
BP神经网络法确定工程材料评价指标的权重
- 2020-12-07下载
- 积分：1
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VC++压缩解压zip文件（支持密码）
1.压缩解压zip格式的，不需要dll或者库文件，支持带密码压缩解压2.：解决当解压加密过的zip时，如果文件经过了压缩，那么解压后的文件会缺少最后的12字节;3.如果文件没有经过压缩（也就是直接打包的方式），会造成死循环4.开发环境VS2008
- 2020-12-03下载
- 积分：1
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