Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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现代水电厂计算机监控技术与试验.pdf
现代水电厂计算机监控技术与试验.pdf电为斌验转花丛书丛书主編文伯姜龙华现代水电厂饼算机监控赦术与试验方辉歌主编换冲主申中力归版www.Ccepp+omm.ch内了单雄多年来赛电力试验的最验,促进道电力试水平的提,中■电力企歌食会电力式验研究分金初中国咖力出组机罩了《找术凸#》,本书电力公司电紫[9】430号文《芋鬼力工业效木些督工作意的要求1用性、先性、扰性代京唱广计算了控技术与试》是本丛书之一,是一本全河反唤我水电厂自动羊害排暂查于综耄来夜棵了技柔节技意蓝技术的全过在理论面。对:分布暴能(包找对分款功分矿等单控、开欺、国向对康、斯平白暴我等邮进行了讨论在工曇实方,购常肌水坐,还对御量水控水电厂监控技术行了嫌讨。并对教件可性与件测式及堂谁认安在等业鹭书龄简5坏环是酚鉴哥始防录了《水电厂无人值赛的着干蠣定、《水幽厂计赛祖监控电厂开设膏状工的等?小最堂事射中苹水咆厂切档内赛,以方动化、站自调化进■业术是具生套考健肾,也可你为者美于业邮训矿团书在版麴目〔CP)据现代水电厂计算机监控技术与试验/方辉钦主编.北京:中国电力出版社,2004电力试验技木丛书/文伯瑜,姜龙华丛书主编}IS75083-19427I.现Ⅱ.方,Ⅲ.水力发电站-计算机控制ITv736中國版本图书馆CP效据核字(2003)第12217号中国电力出版社出版、发行北京兰里河路6号1004hp://www,cpp,com,en)航远印刷厂印刷各地新华书店经售204年3月第一版2004年3月北京第一次印刷毫米ⅹ10y毫米16开本2T即张609千字印数01-300册定价到00元煆杈专有印必究本书如有印装质量问题,我杜发行部负责退换1998年作者于三峡大坝基坑工程工地作者简介方辉钦,教授级膏级工程师,1962年毕业于华中工学院(现华中科技大学),1965年同校研究生毕业。曾在中国水利水电科学研究院、水电部第十二工程局设计院、国电自动化研究院工作,先后担任能源部南京自动化研究所学术委员会委员,自动控制研究所副总工程师,江苏省微电脑应用协会工业控制专委会主任,《水电厂自动化》网刊主编,国家电力公司发输电运营部发电设备改造咨询专家组专家、水电厂“无人值班”(少人值守验收专家组专家等职,现为中国水力发电工程学会理事,江苏省微电脑应用协会理事,中国电机工程学会高级会员,1981年被评为南京市先进工作者,1993年开始享受中华人民共和国国务院颁发的政府特殊津贴主持或作为课题负责人完成了有关葛洲坝、三峡等多个国控和部控重大科研项目,全国试点工程和中外合作项目,已合作编写了《现代水电厂自动化》、《中国水力发电工程机电卷》、《水电厂近代技术》三本书,在国家核心期刊、重点专业期刊和国际、全国学术会议上发表中、英文学术论文50多篇,其中部分被英、俄文文摘收录。参与的项目或图书曾获得部信息成果一等奖、部科技成果二等奖、科技进步奖(科技著作)一等奖和第五届国家图书奖等。电力试验技术丛常编县会主任赵鹏主编文伯瑜副主编姜龙华委员(按姓氏笔画为序)毛兴其王启全王海林白云庆白立江冯亚民史更林朱国俊巩学海刘韶林张大国张方祁太元宋志毅张怡荣张俊生张勇刚李建勋李晨余维平苑立国杨华陈坚林韩施冲赵伟赵庆波郑松赵炳松袁日秋贾玉堂顾南峰徐润生康健傅伟潘言敏““##电力试验研究是经济建设尤其是电力工业发展中一项不可或缺的事业。中外电力事业的发展,均离不开电力试验研究人员的智慧和辛勤工作。新中国成立后,尤其是改革开放以来,随着电力工业的发展,我国电力试验研究事业取得了长足的进步,电力试验研究队伍不断扩大,试验研究成果层出不穷,极大地推动了电力工业的快速发展目前我国各地区均拥有自己的电力试验研究机构,从事电力试验研究的工程技术人员超过1000人。这支队伍的文化层次也从解放初期的以中专、大专毕业生为主,提高到今天的以大学毕业生、硕士生和博士生为主。更重要的是,这是一群热爱自己的事业、勤于钻研、勇于实践的勤奋劳动者。前后几辈人相互学习,长期工作实践,积累了大量试验研究工作经验。这是他们用汗水、心血以至生命换来的、值得用文字记录并传之于后世的宝贵经验。随着电力体制改革的不断深化,使电力试验研究事业进入了竞争激烈同时又是历史上最好的发展时期。电力试验研究同行们愿意把自己的经验无私地奉献给广大读者,就是为了促进我国电力试验研究事业的进步与飞跃,促进我国电力工业的发展与兴旺,进而促进我国国民经济的增长与繁荣。本着各取所长、共同提高的初衷,我们经过长时间的准备,编辑出版《电力试验技术丛书》,相信它一定会给读者带来启发、思考和收益。华北电力科学研胶有限煮任公司总经理和m中国电力企业联合会电力试验研究分会会长2003年12月蚕营我国目前装机总容量为3.5亿kW,居世界第二。随着三峡电站机组的分批投入运行和西电东送工程的推进,到2010年全国性的大电网将初步形成。全国性电力系统运行的动态品质、安全稳定和经济性的改善与提高成为电力科技工作者肩负的重要责任。为了总结多年来我国电力试验的经验,促进我国电力试验水平的提高,中国电力企业联合会电力试验研究分会和中国电力出版社决定组织编写一套《电力试验技术丛书》,以满足国内各电力试验研究院(所)、电厂、供用电企业、电力基建单位及大专院校、科研院所对专业技术书籍的迫切需要。本系列丛书的内容主要是根据原国家电力公司电安生[1996]430号文《关于电力工业技术监督工作规定》的要求而确定的。该文中规定,“电力技术监督工作应以质量为中心、以标准为依据、以计量为手段,建立质量、标准、计量三位一体的技术监督体系,依靠科学进步,采用和推广成熟、行之有效的新技术、新方法,不断提高技术监督的专业水平”。因此,本套丛书涵盖的内容应包括电能质量、金属、化学、绝缘、热工、电测、环保、继电保护、节能等,并对设备的健康水平及其安全、经济运行方面的重要参数、性能与指标进行监督、审查、调整和评价。本丛书共分15册。丛书具有科学性、实用性、先进性、权威性。作者在写作过程中树立了精品意识和创优信念。特别感谢中国电力企业联合会电力试验研究分会,全国三十二个试验研究院(所、技术中心)的领导,我们的分册主编主要由这些单位的技术专家担任。特别感谢中国电机工程学会在组织编写中给予的大力支持。丛书主编怕翔丛书副主编姜也坪2003年12月1日本书作者在一年前就告诉我正在写一本关于水电厂计算机监控技术方面的书,我当即就表示支持并给予肯定。现在他又希望我为此书写一序,我也欣然同意。方辉钦同志原是我校(原华中工学院,现名华中科技大学)20世纪60年代为数不多的研究生之一,当时按原苏联副博士的教学要求培养,打下了良好的专业基础。三十多年来一直在水电厂自动化领域的第一线从事科研和试制工作,经历了我国水电厂计算机监控技术走向成熟的过程。曾经参加了获得中国第五届图书奖的《中国水力发电工程》之第六卷(机电卷)等三本书的编写工作,在20世纪80年代与王金生合著的《现代水电厂自动化》一书成为我国水电厂计算机监控技术的第一本专业性高级科普读物。现在本书即将出版,我为这本全面反映我国水电厂自动化行业的迅速发展和最新成果的专著的问世表示祝贺和欣慰。该书的主要特点是内容丰富,涵盖了水电厂监控使用的各种新技术,对我国水电厂监控技术发展的主要过程、不同时期各种技术发展的情况、代表产品和现状全面地进行了介绍。除常规电站外,涉及梯级、蓄能、无人值班、综合自动化、状态检修等各个方面。作者在理论研究方面作了大量工作。书中对分布系统(包括按对象分布、按功能分布等)、分层控制、开放系统、面向对象、跨平台系统等在理论上都进行了探讨,并对监控系统内部通信、外部通信、现场总线以及We浏览等都进行了讨论,同时概括了各种常用的通信规约和多种现场总线协议及应用情况,还总结了丰富的工程实践经验,理论结合实际,对软硬件试验也进行了讨论,如软件可靠性与软件测试,监控系统环境,监控系统的试验、验收及远方诊断,以及监控系统软件开发环境等。可见,这是一本兼顾学术性、工程性、系统性、实用性和前瞻性于一体的一本不可多得的好书。21世纪待建的水电工程最多的是在中国,该书的出版为总结完善中国的水电厂监控技术作了一份有益的工作。中国工程院院士多多(2003年5月本书雹管我国水电厂计算机监控技术的发展,走过了一条曲折而不平坦的道路。新中国成立后虽然我国的水电事业有了突飞猛进的发展,水电厂自动化技术的发展仍然缓慢。我国执行改革开放政策以后,1979年“全国水电站自动化技术经验交流会”的召开,对我国水电厂自动化技术的发展起到了很好的动员和推动作用。正如本书所总结的,我国水电厂计算机监控技术的发展大体上经过了探索、试点、推广、提高四个阶段。在这次会议以前的探索阶段,当时虽进行了“巡回检测”、“成组调节”、“四遥”等装置以及计算机控制技术的研究,但由于主计算机可靠性低、系统抗干扰等问题难以解决以及监控系统功能设计、设备选配、软件组织等问题而成果甚微。水电厂自动化科学技术发展七年规划(1979~1985年)的制定开始了我国水电厂监控技术发展的试点阶段。随后四个试点工程葛洲坝、富春江、浑江梯级和永定河梯级的科研工作开始启动。在试点工作取得成功以后,1987年在南京召开的“全国水电厂自动化技术总结和规划落实工作会议”和1993年在成都召开的“全国水电厂计算机监控系统工作会议”启动和落实了推广工作,分别安排了“七五”期间14个新建水电厂和12个已运行电厂启动或实现计算机监控系统的研制工作,规定“八五”期间应有40个左右大型电厂(群)实现计算机自动经济运行及安全监视,并规划到2000年大型水电厂和集中管理的梯级电站(群)都应实现不同程度的计算机监控,预期21世纪初全国大中型水电厂总装机容量的70%左右实现不同程度的计算机监控。根据2002年的统计,全国实现计算机监控的水电厂已达300座左右。原电力部安生司主持召开的1994年太平湾会议和1996年湖南会议在推广的基础上开始了“提高”的进程,提出了水电厂实现“无人值班”(少人值守)的目标。在全国水电厂和调度中心(局)的大力支持下,截止到2002年上半年,我国已有30座水电厂通过了电力工业部或国家电力公司组织的正式验收,总装机2192万kW,约占全国水电总装机的30%。在水电厂计算机监控技术的发展中,国电自动化研究院、中国水利水电科学研究院以及其他一些教学、科研、制造单位都发挥了重要的作用。方辉钦同志20世纪60年代起从事水电厂自动化领域的研究工作,曾参加电力系统水电厂经济调度计算机系统的研制和富春江水电厂综合自动化方案的制定,来院后是我院筹建时期自动控制小组七人成员之一。他参加了水电部为制定我国20世纪70年代水电厂自
- 2020-12-09下载
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