RBM 算法理解
RBM 算法理解 这份笔记参考了很多网上的资源，也加入很多自己的理解和详细推导， 非常适合初学者使用， 这篇笔记属于复合型产物，感谢那些网上无私奉献自己心得的人们。RBM能量模型这里说一下RBM的能量模型,这里关系到RBM的理解能量模型是个什么样的东西呢?直观上的理解就是,把一个表面粗糙又不太圆的小球,敚到一个表面也匕较粗糙的碗里,就随便往里面一扔,看看小球停在硫的哪个地方。一般来说停在碗底的可能性比较大,停在靠近碗底的其他地方也可能,甚至运气好还会停在碗口附近(这个碗是比较浅的一个碗):能量模型把小球停在哪个地方定义为一种状态,每种状态都对应着个能量,这个能量由能量函数来定义,小球处在某和状态的概率(如停在碗底的概率跟停在碗口的慨率当然不一样)可以通过这种状态下小球具有的能量来定义(换个说法,如小球停在了碗∏附近,这是·种状态,这个状态对应着一个能量,而发生“小球停在碗口附近”这种状态的概率,可以用来表小,表小成,其中是能量函数),其实还有一个简单的理解,球在碗底的能量一般小于在碗边缘的,比如重力势能这,显然碗底的状态稳定些,并且概率大些,就是我认为的能量模型。1.概率分布函数。各个节点的取值状态是概率的、随机的,这里用了3种概率分布来描述整个RBM网络,有联合概率密度,条件概率密度和边缘概率密度2.能量函数。随机神经网络的基础是统计力学,差不多思想是热力学米的,能量函数是描述整个系统状态的一种测度。系统越有序或者概率分布越集中(比如小球在碗底的情况),系统的能量越小,反之,系统越无序并且概率分布发散(比如平均分布),则系统的能量越大,能量函数的最小值,对应着整个系统最稳定的状态RBM能量模型的作用是什么呢?为什么要弄清楚能量模型的作用呢?第一、RBM网终是一种无监督学习的方法,无监督学习的目的自然就是最大限度的拟合输入数据和输出数据。第二、对于组输入数据来说,如果不知道它的分布,那是非常难对这个数据进行学习的。例如:如果我们实现写出了高斯函数,就可以写出似然睬数,那么就可以进行求解,就知道大致的参数,所以实现如果不知道分布是非常痛苫的·件事情,但是,没关系啊,统计力学的一项硏究成果表明,任何概率分布都可以转变成基于能量的模型,即使这个概率分布是未知的。我们仍然可以将这个分布改写成能量函数第三、能量函数能够为无监督学习方法提供个特殊的东两)日标函数b)标解换句话说,使用能量模型使得学丬一个数据的变得容易叮行了。能否把最优解的求解嵌入能量模型中至关重要,决定着我们具体问题求解的好坏。能量模型要捕获变量(这里我理解的是各个分量之间的关系)之间的相关性,变量之间的相关程度决定了能量的高低。把变量的相关关系用图表是一个图,以概率为测度,所以是概率图)模型的能量模型。由上面所说,RBM是一种概率图模型,既然引入了概率,那么就可以通过采样技术来求解,在CD( contrastive diⅳ vergence)算法中采栟部分扮演着模拟求解梯度的角色。能量模型需要定义一个能量函数,RBM能量函数如下:()=∑∑∑∑这个式子的含义非常明显,每个节点有一个能量, hidden和wsbe之间的连接也有个能量,如何求解呢?如果ⅵ isible有组取值(1,0,1),对应的 hidden取值是(1,0,1,01,0,分别带入上面的公式,最后得到的结果就是能量,这里要注意到()里面的地位是相等的,不存在先后顺序,这是一个结构整体的能量值为什么要搞能量函数?前面指出未知分布不好求解但是可以通过能量函数米表示,那么能量函数的概率模型很大程度上可以得到未知分布的概率模型,这样大致就知道了未知分布的分布既然知道了—个RBM网络 hidden和 visible整个框架的能量函数,那么可以定义这个能量函数(能量)出现的概率,很显然这个能量的出现与 hidden和sbe的每个节点的取值都有关系,那么这个能量出现的概率就是和的联合概率密度里可以将能量函数理解成小球在碗里面具体的一个位置所具有的一个能量,那么联合概率密度就是能量也就是这个状态出现的概率)这个概率不是随便定义的,是有统计热力学解释的定义了联合概率密度,那么我就可以得到一个分布,现在再回来前面的知识,可以得到1最初是未知分布的数据,求解参数,完全无从下手2.将未知分布的数据与能量函数联合在起3定义这个能量函数出现的概率,其实也就是对应着未知分布数据一个函数出现的概率4我们可以得到能量函数的概率分布,这个分布就叫 Gibbs分布,这里不是一个标准的Gibs分布,而是一个特殊的 Gibbs分布,这个分布有一组参数,其实就是能量函数中的那儿个前面知道∫下面可以得到边缘概率密度和()∑∑也可以得到条件概率密度和∑∑从概率到极大似然上面的内容已经得到了Gb分布的各种概率密度函数,现在回到最初的目的,即求解让RBM网络表示的Gibs分布最大可能的拟合输入数据,或者换一种说法,求解的目标可以认为是让RBM网终表示的 Gibbs分布与输入样本的分布尽可能的接近现在的小问题是“最大可能的拟合输入数据"这句话怎么定义:假设表小样本空间,即里面含有很多个不同的,是输入样本的分布,()表示训练样本的概率,再假设是RBM网络表示的 Gibbs分布的的边缘分布,即可以理解成每种不同情况的都对应着一个概率。输入样本的集合定义为,那么样木真实的分布和RBM网络表示的边缘分布的KL距离就是2者之间的差异性(KL的详细讲解见附录),样本的真实分布(什么是样本的分布?见附录)与RBM网络表示的边缘分布的KL距离如下所示()20)-0=2()0)2()(如果输入样本表小的分布与RBM表小的Gbbs分布完全符合,这个KL距离就是0,否则是一个大于0的数山附录对熵的定义(在KL讲解里面)可知,上面)的第一项是输入样本的熵,这个是·个固定的数,输入样本固定了,熵就固定了,第二项明显无法直接求。由KL的性质可知,KL是一定大于0的,那么当第二项最大的时候,整个KL最小,我们本来的日的也是求KL最小。注意到第二项-∑()()中的()当样木固定的时候,是固定的而函数是递增的,即当∑()最大即可。在实际应用中,我们采用的是∑(),其中是样本的个数。这里的-∑()就是极大似然估计(这里大家可以∈代替了∈Ω,这是为什么呢?拿一个2维向量来说,(1,0),(1,1),(0,0)这3个的概率和是1,(0,1)出现的概率是0,那么样本空间是(1,0),(1,1),(0,0),但是我们采样的时候只采样到∫(1,0),(1,1),那么这次的输入样本的集合就是(1,0)(1,1))。结论就是求解输入样本的极大似然,就能让RBM网络表示的 Gibbs分布和样本本身表示的分布最接近。求解极大似然这里对似然的定义参考我的另一篇笔记EM算法这个样本从所有样本被取到的概率为0)=∏(b)b∈6()=(0)=∑(0)c⊙在RBM模型中,上面的似然函数写成(上面的式子中是样本,也可以理解为一个isbe节点):(O)-(0)-l()O∈()=∏(b)=∑()0∈对这个函数进行求导02(066∈⊙66我们由能量模型应该也知道了()的概率∑,那么下面开始求导∑06∑c8上面这个式子一定要注意一个问题,即第一项的和第二项的00是不一样的。第一项的是固定的里面的取多少它就取多少而第二项里面的是所有可能的,其实这个细节也可以从∑和∑中发现出来()注意到()和,上面的式子可以写成∑0606∑()∑x((2m0)2x(2m0606第一项和第二项分别是和的期望,这2个是不同的,第一060个求在下的期望,第二项求的是这个函数在概率()下的期望。将O和()由最前面的东西代换,可得到以下3个式了∑∑∑∑∑∑()∑∑()∑()∑∑(这里用到了一个技巧∑这里∑是指hden中第个向量为0,其他分量的值任取的一组向量。?岁∑()∑()∑()∑()∑∑∑∑)-∑()-∑∑()()-∑()∑()∑∑=∑()-∑∑()()=∑()-∑()∑())-∑()(可以发现和的第二项都含有∑,这意味着要对进行遍历,这明显不可能,但是算梯度需要怎么小呢?这时就可以通过 markov采样来算,只要抽取一堆样本,这些样本符合RBM网络表示的Gibs分布,就可以把上面3个偏导数算出来。具体的处理过程是对于每个训练样本,都用某种抽样方法抽取一个对应的,这个是符合RBM网络所表示的Gbs分布的。那么对于整个训练集{米说,就得到一组对应的符合RBM网络表示的Gibs分布的样本集{然后拿这个样本去估算第二项∑,那么梯度就可以用以下的式了来近似了:()(=)-∑()(=)-∑()上面的式子中表小第个训练样木,是所对应的符合RBM网络表小的Gs分布的样本,在式子中用表示。梯度求出来了,就可以求解了,最后不断迭代就可以得到
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Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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