verilog_IEEE官方标准手册-2005_IEEE_P1364
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group
- 2020-12-11下载
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ESP8266-12E说明书
esp8266-12E的说明书，PDF文档，其他地方不大容易找的。EsP-12E规格书目录1.产品概述21.1.特点1.2.主要参数………垂4由非垂·······:·2.接口定义……4573.外型与尺寸……4.功能描述41. MCU4.2.存储描述99994.3.晶振4.4.接口说明………………104.5.最大额定值4.6.建议工作环境……114.7.数字端口特征115.RF参数126.功耗……………137.倾斜升温……148.原理图…非垂非9.产品试用16深圳市安信可科技有限公司http://www.ai-thinker.comEsP-12E规格书1.产品概述ESP-12EWFⅰ模块是由安信可科技开发的,该模块核心处理器ESP8266在较小尺寸封装中集成了业界领先的 Tensilica l106超低功耗32位微型McU,带有16位精简模式,主频支持80MHz和160MHz,支持RTOS,集成Wi- FI MAC/BB/RF/ PA/LNA,板载天线。该模块攴持标准的IE802.11b/g/n协议,完整的τcPP协议栈。用户可以使用该模块为现有的设备添加联网功能,也可以构建独立的网络控制器ESP8266是高性能无线SOC,以最低成本提供最大实用性,为WⅰFi功能嵌入其他系统提供无限可能。射频MAC接口接收模拟接收匚寄存器」SPI射频CPU内核发射模拟发射心成帧器GPIO加速器12C锁相环H(co)12锁相环电源管理晶振偏置电路SRAM电源管理图1ESP8266EX结构图ESP8266EX是一个完整且自成体系的WF网络解决方案,能够独立运行,也可以作为从机搭载于其他主机McU运行。ESP8266EⅩ在搭载应用并作为设备中唯一的应用处理器时,能够直接从外接闪存中启动。内置的高速缓冲存储器有利于提高系统性能,并减少內存需求。另外一种情况是,ESP8266EX负责无线上网接入承担WiFi适配器的任务时,可以将其添加到任何基于微控制器的设计中,连接简单易行,只需通过SPI/SDO接口或I2 C/UART口即可。ESP8266EX强大的片上处理和存储能力,使其可通过GPIO口集成传感器及其他应用的特定设备,实现了最低前期的开发和运行中最少地占用系统资源。ESP8266EⅩ高度片内集成,包括天线开关 balerη、电源管理转换器,因此仅需极少的外部电路,且包括前端模组在內的整个解决方案在设计时将所占PCB空间降到最低。深圳市安信可科技有限公司http://www.ai-thinker.com2EsP-12E规格书有ESP8266EⅩ的系统表现出来的领先特征有:节能在睡眠/唤醒模式之间的快速切换、配合低功率操作的自适应无线电偏置、前端信号的处理功能、故障排除和无线电系统共存特性为消除蜂窝/蓝牙/DDR/ LVDS/LCD干扰。11.特点80211b/g/n·内置 Tensilica l106超低功耗32位微型McU,主频攴持80MHz和160MHz,支持RTOS·内置10bit高精度ADC内置TCPP协议栈内置TR开关、 balun、LNA、功率放大器和匹配网络内置PL、稳压器和电源管理组件,802.11b模式下+20dBm的输岀功率A-MPDU、A-MSDU的聚合和0.45的保护间隔WiFi@2.4GHz,支持 WPA/WPA2安全模式支持AT远程升级及云端OTA升级支持 STA/AP/STA+AP工作模式支持 Smart Config功能(包括 Android和iOs设备)HSPI、UART、I2C、I2S、 IR Remote Control、PWM、GPIo深度睡眠保持电流为10uA,关断电流小于5uA2ms之内唤醒、连接并传递数据包·待机状态消耗功率小于1.0mW(DTM3)工作温度范围:-40℃-125°C深圳市安信可科技有限公司http://www.ai-thinker.com3EsP-12E规格书12.主要参数表1介绍了该模组的主要参数。表1参数表类别参数说明无线标准80211b/g/n无线参数频率范围24GHz-25GHz(2400M24835M)数据接口UART/HSPL/I2C/I2S/Ir Remote ContorlGPIO/PWM工作电压30~36V(建议3.3V)工作电流平均值:80mA工作温度40°~125硬件参数存储温度常温封装大小16mm x 24mm x 3mm外部接口N/A无线网络模式station/softAP/SoftAP+station安全机制WPA/WPA2加密类型WEP/TKIP/AES升级固件本地串口烧录/云端升级/主机下载烧录支持客户自定义服务器软件开发软件参数提供SDK给客户二次开发Ipv4, Tcp/udp/Http/ftp网络协议AT+指令集,云端服务器, Android/iOS APP用户配置深圳市安信可科技有限公司http://www.ai-thinker.com4EsP-12E规格书2.接口定义ESP-12E共接出18个接口,表2是接口定义。图2ESP-12E管脚图. RXDEN(CH-PD..GPIOSGPIO16.a.. GPIO4ESP-12EGPIO14..D GPIOOGPIo12·。◆GPIo2GPIO13.aD GPIO15ESP 12E表2ESP-12E管脚功能定义序号Pin脚名称功能说明1RST复位模组ADOA/D转换结果。输入电压范围0~1V,取值范围:0~1024EN芯片使能端,高电平有效4IO16GPIO16;接到RST管脚时可做 deep sleep的唤醒5IO14GPIO14: HSPI CLKIO12GPIO 12, HSPI MISOIO13GPIO13 HSPI MOSI: UARTO CTSVCC33V供电CSO片选10MISO从机输出主机输入深圳市安信可科技有限公司http://www.ai-thinker.com5EsP-12E规格书109GPIo912IO10GBIO1013MOSI主机输出从机输入14SCLK时钟15GNDGND16IO15GPIO15: MTDO: HSPICS: UARTO RTS17102GPIo2: UART1 TXD18IOOGPIOO19IO4GPIO420IO5GPIO521RXDUARTO RXD: GPIO322TXDUARTO TXD: GPIO1表3引脚模式模式GPIO15GPIOG PIO2UART下载模式低低局Flash boot模式表4接收灵敏度参数最小小值典型值最大值单位输入频率24122484MHZ输入电阻输入反射-10dB72.2Mbps下,PA的输出功率141516d Bm深圳市安信可科技有限公司http://www.ai-thinker.com6EsP-12E规格书11b模式下,PA的输出功率17.518.519.5d Bm灵敏度DSSS, 1 Mbps98d BmCCK, 11 Mbps-91d Bm6 Mbps(1/2 BPSK93d Bm54 Mbps (3/4 64-QAM)75d BmHT20, MCS7(65 Mbps, 72.2 Mbps)72d Bm邻频抑制OFDM, 6 Mbps37dBOFDM, 54 Mbps21dHT20, MCSO37dBHT20. MCS7dB3.外型与尺寸ESP-12E贴片式模组的外观尺寸寸为16mm*24mm*3mm(如图3所示〉该模组采用的是容量为4MB,封装为SOP-210mi的 SPI Flash。模组使用的是3DBⅰ的PCB板载天线。深圳市安信可科技有限公司http://www.ai-thinker.comEsP-12E规格书图3ESP-12E模组外观CAr个ESP-12E5m2mt3mm图4ESP-12E模组尺寸平面面图表5ESP-12E模组尺寸对照表长宽PAD尺寸(底部)Pin脚间距16 mm24 mm3 mm0.9 mm x 1.7 mm 2 mm深圳市安信可科技有限公司http://www.ai-thinker.com8
- 2020-12-04下载
- 积分：1
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