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C#仓库管理系统
用C#写的仓库管理系统，用SQLserver2008作为数据库，用于管理仓库物品
- 2020-12-08下载
- 积分：1
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可靠性方法：改进一次二阶矩法+Rackwitz-Fiessler方法的Matlab源代码
【实例简介】可靠性算法，改进一次二阶矩法的Matlab源代码，结合Rackwitz-Fiessler方法，能够考虑任意分布的随机变量，里面包含部分测试例子，可直接在Matlab软件中调用执行，文件中包含详细的注释。
- 2021-11-12 00:37:12下载
- 积分：1
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cpci express的标准
目前能找到的cpci express总线的标准ContentsIntroduction1.1 Statement of Compliance131.2 Terminology131.3 Applicable Documents181.4 Objectives…191.5 Name and Logo Usage....翻1E,B面201.5.1 Logo Use201.5.2 Trademark polic201.6 Intellectual Property211.7 Special Word Usage221.8 Connectors1.8.1 Legacy CompactPCI Connectors221.8.2 High -Speed Advanced differential Fabric Connectors1.83 UPM Power Connectors∴…251.8.3.1 System Slot/Board and Type 1 Peripheral Slot/Board.251.8.3.2 Switch Slot/ Board261.8.4 eHM C271.8.5 CompactPCI Pluggable Power Supply Connector271.9 Slot and board descriptions281.9.1 Connector Reference Designators...............311.9.2 System Slot and Board1.9.3 Type 1 Peripheral Slot and Board321.9.4 Type 2 Peripheral Slot and Board331.9.5 Hybrid Peripheral slot351.9.6 Legacy Slot1.9.7 Switch Slot and board.36197.13uSwitchSlotandboard.wwwwwww.361.9.7.2 6U Switch Slot and board371.10 EXample Configurations402 Mechanical Requirements452.1 Mechanical Overview452.2 DrayStandard452.3 Units452.4 Keepout Zones452.5 Connector Requirements.452.5.1 ADF Connectors452.5.1.1 Board connectors452.5.1.3 Backplane Connectors with Hot-Plug Suppor o2.5.1.2 Backplane Connectors without Hot-Plug Support46462.5.2 eHM Connectors462.5.2.1 Board Connector Type Designation.462.5.2.2 Backplane Connectors without Hot-Plug Support .........462.5.2.3 Backplane Connectors with Hot-Plug Support..... 462.5.3 UPM Connectors462.5.3.1 Backplane Connectors…………462.5.3.2 Board Connectors without Hot-Plug Support47PICMG EXPO CompactPCI Express Specification, Draft R. 93, March 11, 2005Do Not design To/Do Not claim compliance To/do Not distribute This specification2.5.3.3 Board Connectors with Hot-Plug Support2.5.4 HM Connectors472.5.5 47-Position Pluggable Power Supply Connector472.6 Chassis Subrack Requirements472.7 Backplane Requirements472.7.1 3U Backplane Dimensions and Connector Locations....... 472.7.2 6U Backplane Dimensions and Connector Locations2.8 Slot Numbering and Glyphs512.9 Board Requirements2.9.1 3U System/Type 1/Type 2 Board Dimensions and ConnectorLocations512.9.2 6U System/Type 1/Type 2 Board Dimensions and ConnectorLocations2.9.3 3U Switch board dimensions and connector locations wwm. 5429.4 6U Switch board dimensions and connector locations.552.9.5 Board pcb thickness562.9.6 ESD Discharge Strip562.9.7 ESD Clip562.9.8 Front Panels562.9.9 CompactPcI Express logo572.9.10 PMC/XMC Support….5729.11 Cross sectional vi582.9.12 Component Outline and Warpage582.9.13 Solder Side Cover(Optional)582. 9.14 Component Heights2.9. 15 System Slot Identification592.10 Rear-Panel 1/0 Board Requirements592.10.1 3U Rear-Panel l/o board dimensions592.10.2 6U Rear-Panel l/o board dimensions3 Electrical Requirements623. 1 Signal Definitions623.1.1 PCI Express Signals.623.1.1.1 PCI EXpress Transmit SigInaIs3.1.1.2 PCI Express Receive Signals623.1.1.3 Interconnect Definition633.1.1.3.1 Link definit633.1.1.3.2 Link Grouping.633.1.1.4 Electrical B643. 1.1.4.1 AC Coupling653.1.1.4.2 Insertion loss653.1.1.4.3 Crosstab‖k3.1.1.4,4 Lane-to-Lane skew3.1.1. 4.5 Equalization673.1.1.4.6 Skew within the Differential Pair(Intra-PairSkew)3.1.1.5 Jitter Budget Allocation683.1.1.5.1 Random Jitter(Rj)683.1.1.5.2 System Level Jitter Distribution693.1.1.5.3 Interconnect Jitter Budget693.1.1.5.4 Eye Patterns703. 1.1.5.5 Type 2 Peripheral Transmitter Eye4PICMG EXPO CompactPCI EXpress Specification, Draft R.93, March 11, 2005Do Not Design To/Do Not Claim Compliance To/Do Not Distribute This specification3.1.1.5.6 Controller Transmitter Eye3.1.1.5.7 Type 2 Peripheral Receiver Eye3.1.1.5. 8 Controller Receiver eye743.1.1.5. 9 Backplane Compliance Testing3.1.1.5. 10 Alternative Controller tX measurement.wm.773.1.1.6 Reference Clock783.1.1.6.1Hot-Pug…...….783.1.1.6.2 Clock Fan-Out..793. 1.1.6.3 Clocking dependencies3. 1.1.6.4 AC-Coupling and Biasing793.1.1.6.5 Routing length803. 1.1.6.6 Reference Clock Specification813.1.1.6.7 REFCLK Phase Jitter Specification3.1.2ESD853.1.35VauX.853.1.4 SMBI3.1.4.1 SMBus " Back Powering Considerations883.1.4.2 Backplane Identification and Capability Using SMBus. 883.1.5 PWRBTN# Signal943.1.6 PS ON# Signal.943.1.7 PWR OK Signal.......953.1.8 WAKE# Signal3.1.8. 1 Implementation Note983.1. 9 PERST# Signal993.1.9.1 nitial Power-Up(G3toL0)……………………1003.1.9.2 Power Management States(so to S3/S4 to so)1013.1.9.3 Power down1023.1.10 SYSEN# Signal…1033.1.11 Geographical Addressing1033. 1. 12 LINKCAP Signal1043.1.13/OPin1043.1.14 Reserved pins1043.2 Hot-Plug Support.1043.2.1 Hot-Plug sub-System Architecture1043.2.2 Power enable1073.2.3 Wake#1083.2.4 Module Power good1083.2.5 Present detection1083.2.6 System Management Bus1083.2.7 System Management Bus alert1083.2.8 Attention LED1093.2.9 Attention Switch1093.2.10 DC Specifications1093.3 Backplane Connector Pin Assignments1093.3.1 System SI3.3.1.1 4-Link Configuration1103.3.1.2 2-Link Combination Configuration3.3.2 Peripheral Slot I ype 11133.3. 3 Peripheral Slot Type 2.1153.3.4 Hybrid Peripheral slot.1153.3.5 Legacy slot117PICMG EXPO CompactPCI Express Specification, Draft R. 93, March 11, 2005Do Not design To/Do Not claim compliance To/do Not distribute This specification3.3.6 Switch Slot1173.3.6.1 3U Switch Slot3.3.6.2 6U Switch Slot x4 Link width1183.3.6.3 6U Switch Slot--X8 Link Width.1213.4 Power Supply Requirements…1233.4.1 Current Available1233.4.2 Regulation and Ripple and noise1243.4.3 Backplane Power Decoupling1243. 4.4 Power Supply Timing1243.4.5 Additional Power Requirements for Boards SupportingHot-Ppluc1254 Keying Requirements4Legacy Slots and Legacy boards12642 eHM Ke126A CompactPCI Express Advanced Differential Fabric Connector......129A 1 General data129A 1.1 Objective of this document.129A.1.2Scope129A.1.3 Intended Method of mounting129A 1. 4 Ratings and characteristics130A.1.5 Normative references130A.1.6 Markings……131A 1.7 Type Designation国131A.1.8 Ordering Information132A 1. 9 Special Connector LoadingsA2 Technical InformationA.2.1 Contacts and terminations133A 3 Dimensional Information134A.3.1 Isometric view and common features.134A 3.2 Engagement Information134A.3. 2.1 Electrical Engagement Length134A.3.2.2 First Contact point135A 3.2.3 Perpendicular to Engagement direction135A.3.2.4 Inclination135A 3.3 Backplane Connectors136A 3.3.1 Dimensions1136A.3.3.2 Contacts136A.3.3.3 Contact Tip Geometry…………137A.3.3,4 Terminations137A. 3. 4 Front board connectors wwwwwwwwwww138A,3. 4. Dimensions.138A 3.4.2 Terminations138A 3.5 Mounting Information for Backplane Connectors138A. 3.5. 1 Hole Pattern on Backplanes139A 3.5.2 Backplane Contact Positional Requirements139A.3.5.3 True position of male contacts.139A.3.6 Mounting Information for Front Board Connectors.140A 3.6.1 Hole Pattern on Printed boards140A 4 Characteristics1416PICMG EXPO CompactPCI EXpress Specification, Draft R.93, March 11, 2005Do Not Design To/Do Not Claim Compliance To/Do Not Distribute This specificationA.4.1 Climatic Category141A 4.1.1 Climatic Category Test batch P: Initial EXamination .....141A 4.1.2 Climatic Category Test Batch A: Mechanical Tests.. 141A 4.1.3 Climatic Category Test Batch B: Harsh Environments. 144A.4.1.4 Climatic Category Test Batch C: Damp Heat146A 4.1.5 Climatic Category Test Batch D: ExtendedEnvironmental Tests147A 4.1.6 Climatic Categary Test Batch E: ExtendedEnvironmental Tests148A.4.2 Electrical characteristics148A.4.2.1 Impedance148A 4.2.2 Crosstalk149A.4.2.3 Propagation Delay149A42.4 Differential skew..149A 4.25 Insertion Loss149BEnriched hard-Metric ConnectorB. 1 General data国面国B150B. 1. 1 Objective of this document150B.1.2 Description of the Connector,s Approach150B.1.3 Descriptive Partitions Found Further This document150B 1.4 Normative References15B 1.4.1 Primary references describing the generic Part ofthe co151B.1.42Additionalreferenceswwwwwww.15B.1.5 Intended Method of Mounting151B 1.6 Markings.152B.1.7 Type Designation(General)152B2 Technical Information∴152B 2.1 Definitions152B 2.2 Contacts152B 2.3 Contact Performance Level154B 2.4 Keying154B.2.4.1 Mating rules155B.2.4.2 Examples for mating and nonmating configurations . 156B.2.5 Type Designation156B 2.6 Applicational Information157B 2.6.1 Alignment and Gathering157B26.2 Polarization翻面面∴158B3 Dimensional InformationQB.3.1 General158B.3.2 View and common features158B3.3 Remarks on Mating Properties of eHM Connector…………159B 3. 4 Fixed Board connector160B 3.4.1 Dimensions160B 3.4.2 TerminationsB.3.4.3 Mounting Information for Fixed Board Connectors..161B 3. 4.4 Hole pattern on fixed board161B.3.4 5 Position of connectors on fixed board∴161B 3.5 Free board connectors162B 3.5.1 Dimensions162B 3.5.2 Termination163PICMG EXPO CompactPCI Express Specification, Draft R. 93, March 11, 2005Do Not Design TO/Do Not Claim Compliance To/Do Not Distribute This specificationB.3.5.3 Mounting Information for Free Board Connectors. .......163B 3.5.4 Hole pattern on free board163B 3.5.5 Position of connectors on front board163B4 Characteristics81.163B.4.1 Climatic Category∴163B 4.2 Electrical Characteristics163B.4.2. 1 Creepage and clearance Distances163B 4.2.2 Voltage Proof164B.4.2. 3 Current-Carrying Capacity.164B.4.2.4 Contact resistance.……164B 4.2.5 Insulation Resistance.164B 4.3 Mechanica164B.4.3.1 Mechanical Operation.164B.4.3.2 Engaging and Separating Forces164B 4.3.3 Contact retesert164B 4.3.4 Static Load. Transverse.164B 4.3.5 Gauge Retention Force.164B 4.3.6 Vibration(Sinusoidal.164B 4.3.7 Shock164B 4.3.8 Polarization method165B.4.3.9 Robustness and effectiveness of coding device .........165B.4.3.9.1 Conditions According to IEC60512-7,Test 13e....B165B 5 Test schedule165B.6 Quality Assessment Procedures…………….…..….…......…...165c Universal Power Connector(UPM)166C 1 General data.I....8.4.4面面面..166C.1.1 Objective of this document166C2 Dimensions167C 3 Perpendicular to Engagement Direction169C4 Inclination169C 5 Mounting Information169C 6 Climatic Category.171Figuresg1-1 HM Connectors231-2 Advanced Differential Fabric(ADF) Connector241-3 UPM Power Connector for System and Type 1 Peripheral Slots/Boards..251-4PowerConnectorforswitchslots/boardswwwwww.26-5 eHM Connector1-647- Position CompactS| Pluggable Power Supply Connector……….281-7 CompactPCI Express 3U Slot Examples29-8 Compact PCI Express 6u Slot Examples301-9 System Board311-10 System Slot321-11 Type 1 Peripheral Board321-12 Type 1 Peripheral Slot.331-13 Type 2 Peripheral Board-14 Type 2 Peripheral Slot34PICMG EXPO CompactPCI EXpress Specification, Draft R.93, March 11, 2005Do Not Design To/Do Not Claim Compliance To/Do Not Distribute This specification1-15 Hybrid Peripheral slot351-16 Boards Supported By Hybrid Peripheral Slots361-17 3 Switch Board371-18 3 Switch Slot371-19 6U Switch board38-20 6U Switch Slot391-21 Backplane with Hybrid Peripheral Slots and Legacy Slots401-22 Backplane with all Hybrid Peripheral Slots411-23 Backplane with Type 2 and Hybrid Peripheral Slots421-24 3U Backplane with Switch, System, Type 1, and Type 2 Slots1-256 U Backplane with Switch, System,Type1, and type2S∴………43442-1 Backplane Overall Dimensions482-2 30 Backplane connector Locations492-3 6U Backplane Connector Locations502-4 board compatibility glyphs2-5 Glyph for Boards that Operate in Either System or Peripheral Slots512-6 Slot Compatibility Glyphs……512-7 3U System, Type 1, and Type 2 Board Dimensions and ConnectorLocations522-8 6U System/Type 1/Type 2 Board Dimensions and Connector Locations...532-9 3 Switch board Dimensions and connector locations542-106uswItchboarddimensionsandconnectorlocations..w.wwwwww.552-11 Modification to PCB to Support Thicker Boards562-12 CompactPCI Express Logo572-13 Alternate CompactPC| Express Logo....….….…572-14 Approximate Clearance Between the PMC/XMC PCB and the aDFConnector………………..572-15 Board cross-Sectional view82-16 3U Rear-Panel l/o board dimensions,602-17 6U Rear-Panel l/o Board Dimensions613-1 2-Link and Loss definition643-2 Backplane Connector Footprint683-3 Interconnect jitter allocation703-4 Peripheral TX Eye Mask723-5 Controller TX eye Mask733-6 Peripheral RX Eye Mask743-7 Controller RX Eye Mask753-8 Backplane TX Compliance signal763-9 Backplane RX Eye…763-10 Alternative Controller measurement783-11 Biasing for HCSL Clock Input3-12 Biasing Simulation Results.803-13 Single-Ended Measurement for swing.833-14 Single-Ended Measurement Points for delta cross point833-15 Single-Ended Measurement Points for Rise and Fall Time Matching ..........833-16 Differential Measurement Points for Duty Cycle and Period833-17 Differential measurement points for rise and fall time843-18 Differential Measurement Points for Ringback843-19 Eight-Slot Backplane Example913-20 Power Supply Timing95PICMG EXPO CompactPCI Express Specification, Draft R. 93, March 11, 2005Do Not design To/Do Not claim compliance To/do Not distribute This specification3-21 WAKE Rise and fall time measurement points983-22 WAKE# Circuit Example93-23 Power Up…1013-24 Power Management states1023-25 Power down1033-26 Typical Hot-Plug Interface Implementation1063-27 4-Link Configuration Backplane Example1103-28 2-Link Combination Configuration backplane example112A-1 Sample Part Number with Explanation132A-2 Special Connector Loading 01001面着国面国B面面国33A-3 View of connectors with common features134A-4 Connector Mating Sequence35A-5 Dimensional Drawing of Backplane Connector.136A-6 Contact Geometry for Zone 2 Backplane Connector137A-7 Dimensional Drawing of Front Board Connectors138A-8 Hole Requirements for backplane Connector139A-9 Backplane Pin Contact Positional Tolerance ................................................140A-10 Hole Requirements for the Front Board Connector140B-1 View of Fixed and Free Board Keying Design(Left Perspective, RightDetailed).……155B-2 View of a Mating and a Non-Mating Keying Combination156B-3 View of fixed and free Board connectors..158B-4 View of Fixed Board connector Including polarization Feature.......159B-5 Dimensional drawing of Fixed board eHM connector160B-6 Hole Requirements for eHM on Fixed Board161B-7 Dimensional drawing of eHM Free Board connector…162B-8 Hole Requirements for eHM Free Board Connector............163C-1 UPM-F-7 Female 7-Position power connector dimensional information 167C-2 UPM-F-5 Female 5-Position Power Connector Dimensional Information ....168C-3 Male 7-Position power connector dimensional information168C-4 UPM-M-5 Male 5-Position Power connector dimensional Information169C-5 Hole pattern for 7-Row male uPm Power connector169C-6 Hole pattern for 5-Row male UPM Power connector170C-7 Hole pattern for female 7-Row uPm Power connector..170C-8Holepatternforfemale5-rowuPmpowerconnectorwwww.171Tables3-1 Interconnect Loss Budget Type 1 Peripheral3-2 Interconnect Loss Budget Type 2 Peripheral653-3 Allowable Interconnect Lane-to-Lane skew673-5 Interconnect Jitter buaget on3-4 Total System Jitter Distribution......69703-6 Type 2 Peripheral Transmitter Eye............713-7 Controller TX Compliance Eye Requirements723-8 Type 2 Peripheral RX Compliance Eye Requirements..733-9 Controller RX compliance Eye Requirements743-10 Backplane TX Compliance Signal (Signal Generator)753-11 Backplane RX compliance eye7610PICMG EXPO CompactPCI EXpress Specification, Draft R.93, March 11, 2005Do Not Design To/Do Not Claim Compliance To/Do Not Distribute This specification
- 2020-12-09下载
- 积分：1
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兴华养猪场管理系统
免费兴华养猪场管理软件，使养猪场管理更加透明、信息化。
- 2020-12-02下载
- 积分：1
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基于改进的种子区域生长法的图像分割（自动选择种子）
在传统SRG算法的基础进行改进，利用颜色空间的像素与其邻域的颜色差异及相对欧式距离自动选择种子；应用SRG技术由已知的种子生长出初始分割区域；根据融合了颜色空间和邻接关系的区域距离对初始区域进行分级合并。
- 2020-11-30下载
- 积分：1
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运用MATLAB软件的海浪仿真，海浪仿真MATLAB程序
运用MATLAB仿真软件采用海浪经验公式对实际的海浪仿真模拟 以用到实际系统中
- 2020-12-05下载
- 积分：1
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支持向量回归
支持向量回归是在支持向量机上进一步的应用，使用支持向量回归可拟合函数
- 2020-12-08下载
- 积分：1
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Vivado约束指导手册
Vivado约束指导手册输入端口到输出端口路径在从输入端口直接到输出端口的路径上,数据:不需要在器件内部锁存(atch),直接从输入端口到输出端口。他们通常被称为ln-to-out数据路径端口时钟可以是虚拟时钟也可以是设计时钟路径举例图3-1描述了上面所有的路径,在此例图中,设计时钟CLKo可被用作端口时钟,这样既可以约束D|N延时也可以约束DOUT延时FPGA DEVICEBoardDeviceInternal Delay REGAData Path DelayREGB Internal DelayBoardDINi DOUT Device○A4InpOutputDelayBUFGPort ClockCLKOPort clockIn-2-out Data PathFigure 3-1: Path Example时钟路径部分每一个时钟路径由三个部分组成:源时钟路径数据路径目标时钟路径源时钟路径源时钟路径是由源时钟从它的源点(典型的是输入端口)到发送时序单元的时钟引脚之间的路径。对于从输入端口起始的时序路径来说,就不存在源时钟路径数据路径对内部电路,数据路径是发送时序单元和捕捉时序单元之间的路径发送时序单元的有效时钟管脚称为路径起始点捕捉时序单元的数据输入管脚称为路径结束点对于输入端口路径,数据路径起始于输入端口。输入端口是路径的起始点对于输出端口路径,数据路径结朿语输岀端口。输岀端口是路径的结束点。目标时钟路径目标时钟路径是由目标时钟从其源点(典型的是输入端口)到捕捉时序单元的时钟管脚之间的路径。对于结束于输出端口的时序路径,就没有目标时钟路径图3-2显示了3段典型的时序路径REGAData PathREGBEndpointSource Clock PathStartpointDestination Clock PathFigure 3-2: Typical Timing PathSetup和Hold分析vⅳ ado ide分析时序并且在时序路径终点时候报告时序裕量。时序裕量是指在时序路径终点数据要求时间和抵达时间的差异。如果裕量为正,从时序的角度考虑此路径是有效的。Setup检查为了计算数据所需的 setup时间,时序引擎:1.决定源时钟和目的时钟之间的普通周期。如果没有被发现,为分析考虑多达1000个时钟周期。2.检查覆盖普通周期上的起始点和终点所有上升和下降沿。3.在任何两个有效 active沿之间的最小正差值dela。这个deta被称为 setup分析的时序路径要求Setup路径要求示例假象2个寄存器之间的一条路径,这些寄存器由其相应时钟上升沿触发。这条路径有效的时钟沿只有上升沿。时钟定义如下:.clko周期6nsck1周期4nsCommon periodclko launch edgesSetup(1)Setup(2)clk1 capture edgesOns 2ns 4nss 8n5 10ns 12nsFigure 3-3: Setup Path Requirement Example图33显示有2个单独的源和目的时钟沿有资格受到 setup分析: setup(1和 setup(2):源时钟发送沿时间:0ns+1*T(ck0)=6ns目的时钟抓取沿时间:0ns+2*(ck1)=8nsSetup Path Requirement=抓取沿时间-发送沿时间=2ns在计算路径要求时候,需要考虑2个重要的点:1.时钟沿是理想的,那就是说,时钟树插入延迟不在考虑之内2.默认时钟在0时间点是 phase-aligned,除非他们的波形定义引进了 phase-shit。异步时钟相位关系未知。时序引擎在分析其间路径时候会考虑默认值。关于异步时钟的更多内容看下部分Setup分析数据要求时间Setup分析数据要求时间是指为了让目的单元能安全的采样数据,数据必须在这个时间点之前稳定。这个值基于:目的时钟采样沿时间.目地时钟延时源时钟和目的时钟的不确定性目的单元 setup时间Setup分析的数据抵达时间Setup分析的数据抵达时间,是指由源时钟发送的数据在路径终点的稳定时候所需要的时间。它的值基于:源时钟发送沿时间源时钟延时数据路径延时数据路径延时包括所有从起点到终点的单元(cel)和线(ne延时。在时序报告中, Vivado将 setup时序考虑为数据路径的一部分。相应的,数据到达和要求时间的公式为:Data Required Time (setup)= destination clock capture edge time+destination clock path delayclock uncertaintyData Arrival Time(setup)= source clock launch edge timesource clock path delay+ datapath delaysetup timeSetup裕量是指要求时间和实际抵达时间的差值:Slack (setup)= Data Required Time -Data Arrival Time在输入数据引脚寄存器上 Setup裕量为负值,说明寄存器有可能锁存到未知的值跳转到错误状态Hod检查Hod裕量的计算与 setup裕量计算直接相关。当 setup分析证明了在最悲观的情况下数据可以被安全捕捉,hold分析确保了:同样的数据不可能被前面目地时钟沿错误的抓取下一个源时钟沿发送的数据不能被用来分析 setup的目的数据沿抓取因此,为了找到hold分析的时序路径,时序引擎考虑了所有为 setup分析的源和目的时钟沿结合的可能。对每一种可能的组合,时序引擎:检查发送沿和减去一个目的时钟周期的抓取沿之间的差值.检查了加上一个源时钟周期的发送沿和抓取沿之间的差值.只保留时间差值最大的发送沿和抓取沿hold路径要求示例采用page33中 setup路径要求示例中的时钟。对于 setup分析那仅有2个可能的时钟沿组合:Setup Path Requirement (S1)=1*T(clk1)-0*T(clk0)= 4nsSetup Path Requirement (S2)=2*T(clk1)-1*T(clk0)=2ns那么相应的hod要求如下:For setup s1:Hold path Requirement (Hla)-(1*T(clk1)-1*T(clk1))-0*T(clko)=onsHold Path Requirement (Hlb)=1*T(clkl)-(0*T(clk0)+I*T(clko))=-2nsFor setup $2:Hold Path Requirement (H2a)=(2*T(clk1)-1*T(clk1))-1*T(clko)2nsHold path Requirement(H2b)=2*T(clk1)-(1*T(clk0)+1*T(clk0))=-4ns从上面可以看出最大的要求时间是Ons,这正好与源时钟和目的时钟第一次上升沿相吻合。Hold路径要求示例,page36显示了 setup检查沿和他们相关的hold检查。cIko launch edgesHla S1 H1b/H2a522bclk1 capture edgesOns 2ns 4ns 6ns 8ns 10ns 12nsFigure 3-4: Hold Path Requirement Example此例中,最终的hod要求时间不是来源于最紧的 setup要求。这是因为所有可能的 setup沿都会被考虑在内,是为了找到最又挑战性的hod要求。正如在 setup分析中,数据要求时间和数据抵达时间是基于以下条件计算的:源时钟发送沿时间.目的时钟抓取沿时间源和目的时钟延时时钟不确定性数据延时.目的寄存器hod时间Data Required Time (hold)= destination clock capture edge timedestination clock path delayclock uncertaintyData Arrival Time (hold)= source clock launch edge timesource clock path delaydatapath delayhold timeHod裕量是要求时间和抵达时间的差值Slack (hold)= Data Arrival Time Data Required Time正的时序裕量意味着即使在最悲观的情况下数据也不会被错误的时钟沿抓取。而负的hold裕量说明抓取的数据错误,而且寄存器可能进入不稳定状态。矫正( recovery和移除( removal分析矫正和移除时序检查与 setup和hold检查相似,区别就是它们应用于异步数据管脚例如set或者clear o对于异步复位的寄存器.矫正时间是异步 reset信号为了锁定新数据已经切换到它的无效状态之后,到下一个有效时钟沿之间的最小时间。移除时间是在异步复位信号安全切换到其无效状态之前,到第一个有效时钟沿之后的最小时间。下面的等式描述了这两种分析的sack是如何计算的Recovery check下面的等式描述了下面如何计算:Data Required Time (recovery ) =destination clock edge start time+ destination clock path delayclock uncertaintyData Arrival Time (recovery )= source clock edge start timesource clock path delaydatapath delayrecovery timeSlack (recovery)= Data Required Time Data Arrival TimeRemoval checkData Required Time (removal)= destination clock edge start timedestination clock path delayclock uncertaintyData Arrival Time (removal)= source clock edge start timesource clock path delay+ datapath delayremoval timeSlack (removal)= Data Arrival Time -Data Required Time正如 setup和hold检査,一个负的 recovery裕量和 remova裕量说明寄存器可能进入亚稳态,并且将未知的电子层带入设计中。定义时钟时钟数字设计中,时钟提供了从寄存器到寄存器之间可靠的传输数据的时间参考。 Vivado ide时序引擎用时钟特征来:计算时钟路径要求以裕量计算的方式报告设计时序裕量更多信息,参考时序分析这章为了得到最精确的最大的时序路径覆盖,时钟必须合理的定义。可以用下面的特征定义时钟:源时钟是指定义在时钟驱动引脚或者时钟树跟端口的时钟时钟沿可以由周期和波形特性的组合描述周期是ns级的,与描述的波形的时间周期相匹配.时钟波形是在时钟周期里,在数ns内时钟上升沿和下降沿绝对时间的列表列表必须包含偶数个值。第一个值一般与第一个上升沿吻合,除非另外指定,默认的时钟占空比是50%相位是ns。如图4-1所示,ck0周期10ns,占空比50%,相位0ns。Ck1周期8ns,占空比75%,相位2ns。CIkO: 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