全志 F1C600完整手册
The F1C600 processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of boombox markets. F1C600 processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C600 supports Full HD video playback, iAllwinnerTechnologyRevision HistoryRevision historyVersionateDescriptionV1.0NoV10,2015nitia|Re|ease∨ersⅰonF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 3AllwinnerTechnologyRevision HistoryTable of contentsDeclaration2Revision histeD。着,着垂Table of contents.:::::.:::::1:4Chapter 1.About This Documentation361.1 Documentation overview36Chapter 2 Overview....372.1 Processor features2.1.1, CPU Architecture2.2. Memory Subsystem....................382.2.1. Boot rom382.2.2 SDRAM382.2.3. SD/MMC Interface..:::··:·.:::::..:·.:::::::::::··:382.3. System Peripheral.382.3.1. Timer.382.3.2.|NT392.3.3.CCU392.3.4.DMA,392.3.5.PWM,392.4. Display subsystem39241. Display engine…,,…...:::::392.4.2. Display output.....39F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 4AllwinnerTechnologyRevision History2.5. Video Engine26.| mage Subsystem…D看看1,翻看、·着国,着,,,面面,2.6.1.CS|4看402.6. 2 CVBS Input402. 7. Audio Subsystem2.7.1, Audio codec2.8. System Peripherals2.8.1.USB2.00TG412.8.2. KEYADC412.8.3.Tl:::::412.8.4. Digital Audio Interface.....................2.8.5.UART412.8.6.SP412.8.7.TW|422.8.8.CIR422.8.9,RSB422.8.10.OWA.422.9 Package422.10. System block Diagram43Chapter3. System..........................,443.1. Memory Mapping….453.2. CCU2463.21 Overy3.2.2, FeatureF10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 5AllwinnerTechnologyRevision History3.2.3. Functionalities Description3.23.1. System bus….:.:::..a...:::::::非3.23.2 Bus clock tree473.2.4. CCU Register List…….473.2.5. CCU Register Description483.2.5. 1 PLL CPU Control Register3.2.5.2. PLL AUDIO Control register......................493.2.5.3. PLL VIDEO Control Register503.2.5.4. PLL VE Control Register513.2.5.5. PLL DDR Control Register3.2.5.6. PLL PERIPH Control Register...............523.2.5.7. CPU Clock Source register533.2.5.8. AHB/APB/HCLKC Configuration Register543.2.5.9. Bus Clock Gating Register O.......553.2.5. 10. Bus Clock Gating Register 1................553. 2.5.11. Bus Clock Gating Register 2563.2.5.12. SDMMCO Clock Register583.2.5.13. SDMMCl Clock Register.58325.14. DAUDIO Clock Register……593.2.5.15. OWA Clock Register.........................593.2.5.16. CIR Clock Register.603.2.5.17. USBPHY Clock Register603.2.5. 18 DRAM Gating register.603.2.5. 19 BE Clock Register61F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 6AllwinnerTechnologyRevision History3.2.5.20. FE Clock Register623. 2.5.21. TCON Clock Register623.2.5.22. De-interlacer Clock Register623.2.5.23. TVE Clock Register∴633.25.24. TVD Clock Register……643.2.5.25. CSI Clock Register643.2.5.26. VE Clock Register.......653.2.5.27. AUDIO CODEC Clock Register653.2.5.28. AVS Clock Register.653.2.5.29. PLL Stable Time register 0653.2.5.30. PLL Stable Time Register 1...............................................................653.2.5.31. PLL CPU Bias register663.2.5.32. PLL AUDIO Bias Register663.2.5.33. PLL VIDEO Bias Register663.2.5. 34 PLL VE Bias Register673.2.5.35.PLL_ DDR Bias Register…..,…,…,…673.2.5.36.PLL_PER| PH Bias Register……673.2.537.PLL_ CPU Tuning Register.……683.2.5.38. PLL DDR Tuning Register683.2.5.39. PLL AUDIO Pattern Control register........................693.2.5.40. PLL VIDEO Pattern Control Register.693.2.5. 41. PLL DDR Pattern Control Register3.2.5.42. Bus Software Reset Register O..3.2.5.43. Bus Software Reset register 1F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservecPage 7AllwinnerTechnologyRevision History3.2.5.44. Bus Software Reset Register 23.2.6. Programming guidelines3.2.6.1.PLL4看3.2.6.2.BUS3.3. Timer743.3 1. Overvi翻着看743.3.2, Feature…743.3.3. Functionalities Description..743.3.3.1. Typical Applications743.3.3.2. Functional block Diagram753.3.4.Timer Register List.......................753.3.5. Timer Register Description3.3.5.1. Timer IRQ Enable Register...763.3.5.2. Timer iRQ Status Register3.3.5.3. Timer 0 Control Register3.3.5.4. Timer o Interval value register .................................3.3.5.5. Timer 0 Current Value Register3.3.5.6. Timer 1 Control Register....3.3.5.7. Timer 1 Interval value register,7933.58. Timer1 Current Value Register…....…793.3.5.9. T imer 2 Control register3.3.5.10. Timer 2 Interval value Register803.3.5. 11 Timer 2 Current Value register3.3.5. 12 AVS Counter Control Register81F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 8AllwinnerTechnologyRevision History3.3.5.13. AVS Counter O Register.81335.14. AyS Counter1 Register.,,…,;…,…,…,…813.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…3.3.5.16. Watchdog irQ Enable Register.………823.3.5.17. Watchdog statusster823.3.5.18. Watchdog Control Register83335.19. Watchdog Configuration Register……,,,…833.3.5.20. Watchdog Mode register....833.3.6. Programming Guidelines843.3.6.1. Timer,,84336.2. Watchdog….…843. 4, PWM853.4.1. Overview853.4.2 Feature853.4.3. Functionalities Description853. 1. Functional Block Diagram......着,着面853.4.4. Operation Principle863. 4.4.1. PWM output pins863.4.5. PWM Register List……3.4.6. PWM Register Description.....................3.4.6.1. PWM Control Register.3.4.6.2. PWM Channel 0 Period Register883.4.6.3. PWM Channel 1 Period register893.5.NTC.90F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 9AllwinnerTechnologyRevision History3.5.1. Overview903.5.2, Feature.:..:.:::::a:::.:::.:.a..:::::.:::::903.5.3. Functionalities Description903.5.3.1. Functional Block Diagram903.5.4.Interrupt source913.5.5. INTC Register List.....................................3.5.6. INTC Register Description…923.5.6.1. Interrupt Vector Register.……923.5.6.2. Interrupt base Address register933.5.6.3. NMI Interrupt Control Register933.5.6.4. Interrupt irQ Pending register o933.5.6.5. Interrupt iRQ Pending register 1...............933.5.6.6. Interrupt Enable register o933.5.6.7. Interrupt Enable Register 1.............933.5.6.8. Interrupt Mask register 0943.5.6.9. Interrupt Mask Register 1.::::943.5.6.10. Interrupt Response Register O.......943.5.6.11. Interrupt Response Register 1943.5.6.12. Interrupt Fast Forcing register 0943.5.6.13. Interrupt Fast Forcing Register 1....................................................................953.5.6. 14 Interrupt Source Priority Register O953.5.6.15. Interrupt Source Priority Register 1...973.5.6.16. Interrupt Source priority register 21003.5.6. 17 Interrupt source priority register 3102F10600 User Manual( Revision 1.0)Copyright O2015 Allwinner Technology. Co, Ltd. All Rights ReservedPage 10
- 2020-11-28下载
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RS纠错编码原理及其实现方法.pdf
RS纠错编码原理及其实现方法。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd前言随着越来越多的系统采用数字技术来实现,纠错编码技术也得到了越来越广泛的应用。RS码既可以纠正随机错误,又可以纠正突发错误,具有很强的纠错能力,在通信系统中应用广泛。近些年来,随着软件无线电技术的发展,RS编码、译码一般都在通用的硬件平台上实现。通常采用基于FPGA的ⅦHDL编码硬件实现,或者在DSP、单片机上用C和汇编编程软件实现。RS纠错编码涉及的领域很广,特别是设计到很多数学知识。这对那些对数学不太感冒的工程技术人员来书是个不小的挑战。尽管讲RS编码的书籍很多但是那些书都是采用循序渐进,逐步引人的方式从汉明码到循环码,从循环码到BCH码,BCH码再引入悶S码。对亍工程技术人员他们需要的是简明扼要的讲解,和详细的实现方法。本人写这篇文章的宗旨就是尽量最简单的语言最简短的篇幅来讲RS纠错编码原理,把重点来放在实现方法上。为了便于读者仿真,本文采样MLAB程序实现,程序尽量符合硬件C语言写法,读者经过简单修改即可应用到工程中去。本文读者对象本文是为那些初识瑙编码的学生、工程技术人员而写,并不适合做理论研究,如果你是纠错编码方面的学者、专家,那么本文并不适合你。由于作者水平有限,错误在所难免,恳请读者批评指正。不得更改陈文礼2008-01于郑州Zhengzhou Oriole Xinda Electronic Information Cc., Ltd必备的一些代数知识1、在纠错编码代数中,把以二进制数字表示的一个数据系列看成一个多项式。例如二进制数字序列1010111,可以表示成:M(x)=ax+a5x0+a5不5+a+4 TasK +ax+a,x+ank式中的x表示代码的位置,或某个二进制数位的位置,X前面的系数表示码的值。若a;是一位二进制代码,则取值是0或1。dM()称为信息代码多项式多项式次数称系数不为0的x的最高次数为多项式/(x)的次数,记为Of(x)2、域域在R编码理论中起着至关重要的作用。简单点说域GF(2)有2设2个符号[0,n,a2…22且具有以下性质域中的每个元素都可以用a",a,a2,om的和来表示。a←la为本原多项式p(x)的根。运算规则有:在纠错编码运算过程中,加减、乘和除的运算是在伽罗华域中进行。现以GF(2)域中运算为例:加法例:a+a=0010+0110101(模2加法相当于0005与011或减法运算与加法相同乘法例:a·a0=a(8+10)modl5除法例:cs/a0=a-2=a-2+5=a不理解没关系,下面的例子也许对你有帮助。例:mF=4,p(x)=x4+x+1求GF(2")的所有元素因为a为p(x)的根得到a4+a+1=0或a4=a+1(根据运算规则)Zhengzhou Oriole Xinda Electronic Information Cc., Ltd由此可以得到域的所有元素元素二进制对应十进制对应码值000000101000a+100l⊥0110a(a+1)=a+a(mod p(a))12a(a+a=a+a(mod p(a)1011a(a+l(modula))+a+1)10C(a+1=a+a(mod p(a )a(a23+a)a+I(mod p(a)1110a(a+a+D=aa+a(modp(a)tatI(mod p(a))11a(a3+a2+a+1)=a34a2+1(modp(a)1001a(a+a+1=a+l(mod p(a)a(a+1=l(mod(a))由此可以看岀本原多项式是求解域的全部元素的关键。读者也许会有这样的疑问我们如何得到p(x)呢?本原多城式p(x)的特性是2+得到的余式等于0O(X由于作者也是工程技术人员,具体怎么得到p(x),也没有深究过。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd作者在设计RS编码时候都是根据 MATLAB指令rsgeηpoly来得到p(x)。其格式为 rsgenpoly(n,k)参数n为码长一般n=2"-1,k为信息码元个数。例如m4,码长n=15,信息码元长度为9GF(2)的本原多项式可以根据指令>>rsgenpoly(15, 9)得到ans= GF(2 4)array. Primitive polynomial =D 4+D+1 (19 decimal)有读者来信问:我要做一个(158的RS编码,在 MATLAB中输入命令 rsgenpoly(158,128),结果MAB报错Error using =- rsgenpolyN must equal 2m-1 for some integer m这里做一下解释我们S编码时普先要根据码长选取mλ选择原则是2若码长为6那么我们可以选择n=8, rsgenpey命令的第少个参数必须为2"-1,第二个参数司以随便选择只要小于2”-1就形了在此给出m∈(2,16)的所有本原多项式(m=2)P[m+1]={1,1,1}/米1+x+x3*/P[m+1]-{1,1,0,1}/米1+x+x4*/P[m11]={1,1,0,0,1}/米1+x2+x5*/P|m+1={1,0,1,0,0,1};Zhengzhou Oriole Xinda Electronic Information Cc., Ltd(m=6)/米1+x+x6*/P[m+1]={1,1,0,0,0,0,1}7)/来1+x3+x7*P[m+1]={1,0,0,1,0,0,0,1}(m=8)/米14x2+x31x4+x8*/P[m+1]-{1,0,1,1,1,0,0,0,1/*1+x4+x9半P[m1]={1,0,0,0,1,0,0,0,(m=10)/1+x3+x10*/P|m+1={1,0,0,1,0,0,0,0,/*1+x2+x11P[m+1]={1,0,0,0,0,0,0,1}(m=12)/*1+x+x4+x6+x12P[m+1]-{1,1,0,0,、1,0,0,(m=13)/*1+x+x^3+x4+x^13*/P[m+1]={1,1,0,1,1,0,0,00,0,1};(m=14)/*1+x+x6+x10+x14来P[m+1]={1,1,0,0,0,0,1,0,0,0,1,0,0,0,1}(m=15)/米14x+x15*/P[m+1]={1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1};(m=16)/*1+x+x3+x12+x16*/P[m+1]={1,1,0,1,0,0,0,0,0,0,0,0,1,0,0,0,1};Zhengzhou Oriole Xinda Electronic Information Cc., Ltd二、线性分组码的一些基本概念1、线性分组码一般用(n,)或(n,k,d)表示n为码长,k为信息码元的数目,n-k为监督码元的数目。d表示码元距离。定义:两个码组上对应位置上数字不同的个数称为码组的距离。发送的码字C=(1,C2C3,…C接收的矢量r=(,2,信道错误图样:e=c+r例如c=(1,1,0,0,0)(1,0,001)e=(1+1,1+0,0+0,0+0,0+1)(0,1,0,0,1)从而可以看出从左端起第2位和第5位是错误的2、校验矩阵概念码长为n,信息数为k,监督数为r。这样的一组码形式为:m:m2,P,P2Pm表示第个信息码,P表示第j个校验码各个校验码可从下列线性方程组求得hm+h2m2+…+n+1B1+012+0h2m1+2m2+…+h2m+0p1p20hmn+h,2m2+…+hm+O+0+…+1p,=0式中h;是常数校验方程组可写成校验矩阵100h21h2…,h2k010h000该矩阵具有r行和n列故式(1-1)可以写成c=0或c=08Zhengzhou Oriole Xinda Electronic Information Cc., LtdH矩阵称为[n,k,r码的校验矩阵。发送矢量为C接收矢量为F若rH≠0则说明接收到的码有错误。设错误图样为e则可写成以下关系式r=c+e为了纠错必须知道那些位上存在错误。这可由校正子(又称伴随式)s来确定s=rH=cH +eh=eh译码器的主要任务就是如何从中得到最像e的错误图样e从而译出c=r-e设第讠个是错误的因此e=(00..0第个有错误s=rH=(00…0、100000)00计算出的矢量示出i是出错误的位置。3、生成矩阵概念生成矩阵G,它是一个k行,n列的矩阵若已知信息组m,通过生存矩阵可求得相应的码字。c=mxG(m是k个信息元组成的信息组)这个应该比较容易理解,在此就不做过多解释。、RS码的一些重要性质1、RS码生成多项式:码长n=2”-1,监督元数目r=n-k=2t,能纠正t个错误。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd定义:在(n,k,d)的RS码中,存在唯一的n-k次多项式g(x),使得每一个码多项式c(x)都是g(x)的倍式。g(x)称为n,k,d]RS码的生成多项式一般情况下g(x)=(x-a)(x-a2)…(x-a2)2、定理:在GF(2m)中,每个非0元素(1,a,a2…a22)均满足x2=1,反之x21-1=0的根必在GF(2")中。所以x-1=(x-a)(x-a)x3、RS码的校验多项式由于生成多项式g(x)是x-1的因式g(rh(g(x)为n-k次多项式,则h(x)为k次多项式,k3x+g)hx+…+x+4)由右式可以看出x"1,x2,x的系数均等于0即gg0010h1+g1bo=0g0h+g1h11+…+8nkh2(2k)=0∴.+n-kk-10n-kk式中g0+81h1+…+8nkh1(n=k)(表示X的系数10
- 2020-12-08下载
- 积分：1
