Xilinx_AXI

代码说明：

说明：  AXI verilog designs with testbench: AXI-lite, AXI, AXI-stream

文件列表：

Xilinx_AXI\hdl\verilog\axi_lite_master.v, 33415 , 2013-05-29
Xilinx_AXI\hdl\verilog\axi_lite_slave.v, 22985 , 2013-05-29
Xilinx_AXI\hdl\verilog\axi_master.v, 31609 , 2013-05-29
Xilinx_AXI\hdl\verilog\axi_slave.v, 24710 , 2013-05-29
Xilinx_AXI\hdl\verilog\axi_stream_master.v, 7284 , 2013-05-29
Xilinx_AXI\hdl\verilog\axi_stream_slave.v, 5921 , 2013-05-29
Xilinx_AXI\ip_repo_complete\vv_index.xml, 6203 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\component.xml, 28258 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\verilog\axi_lite_master.v, 33415 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\xgui\axi_lite_master_v1_0.tcl, 892 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0.zip, 10190 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\component.xml, 24457 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\verilog\axi_lite_slave.v, 22985 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\xgui\axi_lite_slave_v1_0.tcl, 247 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0.zip, 7441 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\component.xml, 38074 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\verilog\axi_master.v, 31609 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\xgui\axi_master_v1_0.tcl, 2117 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0.zip, 11209 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\component.xml, 38903 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\verilog\axi_slave.v, 24710 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\xgui\axi_slave_v1_0.tcl, 1518 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0.zip, 9250 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\component.xml, 14530 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\verilog\axi_stream_master.v, 7284 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\xgui\axi_stream_master_v1_0.tcl, 1563 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0.zip, 5414 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\component.xml, 13864 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\verilog\axi_stream_slave.v, 5921 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\xgui\axi_stream_slave_v1_0.tcl, 946 , 2005-06-25
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0.zip, 4955 , 2013-05-29
Xilinx_AXI\readme.txt, 4567 , 2013-05-29
Xilinx_AXI\source.tcl, 18373 , 2013-05-29
Xilinx_AXI\tb\verilog\axi_stream_system_wrapper_tb.v, 2781 , 2013-05-29
Xilinx_AXI\tb\verilog\axi_system_wrapper_tb.v, 2761 , 2013-05-29
Xilinx_AXI\tb\verilog\lite_system_wrapper_tb.v, 2763 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\verilog, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\xgui, 0 , 2013-05-29
Xilinx_AXI\hdl\verilog, 0 , 2013-04-03
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0, 0 , 2013-05-29
Xilinx_AXI\tb\verilog, 0 , 2013-05-29
Xilinx_AXI\hdl, 0 , 2013-05-29
Xilinx_AXI\ip_repo_complete, 0 , 2013-05-29
Xilinx_AXI\tb, 0 , 2013-05-29
Xilinx_AXI, 0 , 2020-04-20