cic_design
于 2016-12-08 发布
文件大小:3KB
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代码说明：
采用CIC（级联积分梳状）滤波器实现降采样的功能，并分析了级联级数、差分延时数对CIC滤波器幅频响应的影响；采用Verilog语言实现了CIC滤波及降采样的功能；(Using CIC (Cascaded Integrator Comb) filter down-sampling function, and analyzes cascaded stages, affecting the number of differential delay CIC filter amplitude-frequency response using Verilog language of the CIC filter and down sampling Features )
文件列表：
cic_design.v,2085,2016-05-11
CIC_foundation.m,2574,2016-03-20
CIC_Multirate.m,2122,2016-05-04
tbw_cic3.v,1549,2016-05-11
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