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SSI_read
说明： 使用Verilog 编程语言实现对11 bit 编码器SSI输出的读取(Use Verilog to read encoder,it's 11 bit and SSI output)
- 2020-12-28 21:09:01下载
- 积分：1
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AMI AFU For Aptio 4
说明： Software for burn BIOS AMI AFU
- 2019-03-08 16:47:16下载
- 积分：1
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chaoxi
Tide Model Driver可以计算跟预测潮位跟调和常数，里面还有PDF说明书详细介绍了使用方法(Tide Model Driver can be calculated with the harmonic constants with the predicted tide level, there is also a PDF manual details the use of)
- 2011-05-18 09:38:12下载
- 积分：1
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ConHDLFTB_15_5
cadence 培训教程
关于布局布线，期间封装(cadence training)
- 2011-12-27 13:13:47下载
- 积分：1
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ACarrierTrackingAlgorithmBasedOnFPLL
介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化，基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。因此，该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境；同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。(Introduce an approach based on frequency-locking phase-locked loop (FPLL) carrier tracking algorithm. Frequency tracking module can adapt to a larger dynamic range of the frequency change, software-based numerical control oscillator (NCO) module can achieve the very high frequency tracking accuracy. Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. Therefore, the FPLL carrier-based tracking algorithm can be adapted to signal the existence of a larger dynamic range and noise of the application environment at the same time, the PFD algorithm expression is simple, easy to use programmable digital devices.)
- 2008-07-22 15:48:34下载
- 积分：1
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Transmission System
说明： Using the SVS Interface in PowerFactory. There are a number of standard controls for SVS in the library that can be used. You will also find two standard frames in the global library (Refer to LibraryStandard ModelsComposite Model Frames). This approach is used in the attached file SVCExampleWithInterface.pfd, the SVS interface is a PowerFactory element of the class ElmSvsctrl that is setting the number of connected capacitor blocks and the angle of the thyristor control of the reactance. It also initialises the controller output to zero. This should be used with care since the consideration of the SVS control limits will be then offset by the initial SVC admittance. The interface has the advantage that operates the parallel capacitors when required.
- 2019-03-01 21:14:01下载
- 积分：1
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Test_IDL3D
说明： 这是一个用于IDL三维分析的一个源码文件(This is a source file for IDL 3D analysis)
- 2019-11-29 09:00:57下载
- 积分：1
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optimize-
键是一种标准零件,通常用来实现轴与轮毂之间的周向固定以传递转矩，有的还能实现轴上零件的轴向固定或轴向滑动导向。在键连接设计时，间的高度和宽度根据轴的直径d选取，而键长L则根据轴上零件轮毂宽度B而定，通常L=B-（5—10）mm。键的尺寸确定后，再进行强度校核。而为了保证绝对安全，键的尺寸取值往往都趋于保守，所选键的尺寸大。本程序采用优化设计方法，在满足强度要求的前提下求出键的最小结构尺寸，证明键宽b和键高h的取值可以小于标准值。(Key is a standard part, often used to achieve between shaft and hub to transfer torque to a fixed week, and some can achieve a fixed axis or axial parts of the axial sliding direction. Key connection in the design, height and width between the shaft diameter d according to selection, and the bond length L is based on the width of the wheel shaft parts B and, typically L = B-(5-10) mm. Key size is confirmed, then strength check. In order to guarantee absolute security, key size values ??are often conservative, the size of the selected key to big. The program uses optimization methods to meet the strength requirements of the derived key premise of the minimum structure size, proved key width b and height h of the key values ??can be less than the standard value.)
- 2011-09-05 20:16:03下载
- 积分：1
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自适应噪声对消定、变、改进结合.mLMS
包含定步长LMS算法、变步长LMS算法、改进变步长LMS算法，可用于信号的预处理过程(Includes fixed-step LMS algorithm, variable-step LMS algorithm, and improved variable-step LMS algorithm for signal preprocessing)
- 2021-02-25 14:09:38下载
- 积分：1
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UART
基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)
- 2020-06-18 23:20:01下载
- 积分：1
