pingpang_ram

代码说明：

  乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。(Ping pong RAM static random access control, to solve the problem of continuous data flow storage.)

文件列表：

pingpang_ram
............\data_ctrl.v,746,2017-04-19
............\data_ctrl.v.bak,748,2017-04-17
............\db
............\..\altsyncram_ufn1.tdf,13629,2017-04-19
............\..\logic_util_heursitic.dat,0,2017-04-19
............\..\pingpang_ram.cbx.xml,94,2017-04-19
............\..\pingpang_ram.cmp.rdb,4132,2017-04-19
............\..\pingpang_ram.cmp_merge.kpt,220,2017-04-19
............\..\pingpang_ram.db_info,152,2017-04-19
............\..\pingpang_ram.hier_info,22040,2017-04-19
............\..\pingpang_ram.hif,7000,2017-04-19
............\..\pingpang_ram.lpc.html,2827,2017-04-19
............\..\pingpang_ram.lpc.rdb,540,2017-04-19
............\..\pingpang_ram.lpc.txt,2964,2017-04-19
............\..\pingpang_ram.map.kpt,887,2017-04-19
............\..\pingpang_ram.map.qmsg,5361,2017-04-19
............\..\pingpang_ram.map_bb.hdb,8771,2017-04-19
............\..\pingpang_ram.pre_map.cdb,8606,2017-04-19
............\..\pingpang_ram.pre_map.hdb,16849,2017-04-19
............\..\pingpang_ram.rtlv.hdb,16788,2017-04-19
............\..\pingpang_ram.rtlv_sg.cdb,10502,2017-04-19
............\..\pingpang_ram.rtlv_sg_swap.cdb,2745,2017-04-19
............\..\pingpang_ram.sgdiff.cdb,4868,2017-04-19
............\..\pingpang_ram.sgdiff.hdb,15569,2017-04-19
............\..\pingpang_ram.sld_design_entry.sci,211,2017-04-19
............\..\pingpang_ram.sld_design_entry_dsc.sci,211,2017-04-19
............\..\pingpang_ram.smart_action.txt,8,2017-04-19
............\..\pingpang_ram.syn_hier_info,0,2017-04-19
............\..\pingpang_ram.tis_db_list.ddb,187,2017-04-19
............\..\prev_cmp_pingpang_ram.qmsg,5361,2017-04-19
............\greybox_tmp
............\...........\cbx_args.txt,510,2017-04-19
............\incremental_db
............\..............\compiled_partitions
............\..............\...................\pingpang_ram.db_info,152,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.cdb,5937,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.dpi,2403,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.hbdb.cdb,618,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.hbdb.hb_info,46,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.hbdb.hdb,14646,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.hbdb.sig,31,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.hdb,14944,2017-04-19
............\..............\...................\pingpang_ram.root_partition.map.kpt,897,2017-04-19
............\..............\htm" target=_blank>README,653,2017-04-19
............\logic_ctrl.v,2749,2017-04-19
............\logic_ctrl.v.bak,1675,2017-04-10
............\pingpang_ram.done,26,2017-04-19
............\pingpang_ram.flow.rpt,8780,2017-04-19
............\pingpang_ram.map.rpt,15106,2017-04-19
............\pingpang_ram.map.summary,680,2017-04-19
............\pingpang_ram.qpf,1284,2017-04-19
............\pingpang_ram.qsf,4023,2017-04-19
............\pingpang_ram.v,1610,2017-04-19
............\pingpang_ram.v.bak,2195,2017-04-17
............\pingpang_ram_nativelink_simulation.rpt,1003,2017-04-19
............\pingpang_ram_tb.v,543,2017-04-19
............\pingpang_ram_tb.v.bak,0,2017-04-19
............\ram_ip.qip,368,2017-04-19
............\ram_ip.v,9666,2017-04-19
............\ram_ip_bb.v,8017,2017-04-19
............\ram_ip_inst.v,228,2017-04-19
............\simulation
............\..........\modelsim
............\..........\........\modelsim.ini,11131,2017-04-19
............\..........\........\htm" target=_blank>msim_transcript,10606,2017-04-19
............\..........\........\pingpang_ram_run_msim_rtl_verilog.do,1011,2017-04-19
............\..........\........\pingpang_ram_run_msim_rtl_verilog.do.bak,1011,2017-04-19
............\..........\........\pingpang_ram_run_msim_rtl_verilog.do.bak1,1011,2017-04-19
............\..........\........\rtl_work
............\..........\........\........\data_ctrl
............\..........\........\........\.........\verilog.prw,1544,2017-04-19
............\..........\........\........\.........\verilog.psm,4512,2017-04-19
............\..........\........\........\.........\_primary.dat,298,2017-04-19
............\..........\........\........\.........\_primary.dbs,592,2017-04-19
............\..........\........\........\.........\_primary.vhd,366,2017-04-19
............\..........\........\........\logic_ctrl
............\..........\........\........\..........\verilog.prw,3029,2017-04-19
............\..........\........\........\..........\verilog.psm,11768,2017-04-19
............\..........\........\........\..........\_primary.dat,989,2017-04-19
............\..........\........\........\..........\_primary.dbs,2048,2017-04-19
............\..........\........\........\..........\_primary.vhd,516,2017-04-19
............\..........\........\........\pingpang_ram
............\..........\........\........\............\verilog.prw,2497,2017-04-19
............\..........\........\........\............\verilog.psm,6520,2017-04-19
............\..........\........\........\............\_primary.dat,1033,2017-04-19
............\..........\........\........\............\_primary.dbs,2350,2017-04-19
............\..........\........\........\............\_primary.vhd,310,2017-04-19
............\..........\........\........\pingpang_ram_tb
............\..........\........\........\...............\verilog.prw,1745,2017-04-19
............\..........\........\........\...............\verilog.psm,6408,2017-04-19
............\..........\........\........\...............\_primary.dat,505,2017-04-19
............\..........\........\........\...............\_primary.dbs,843,2017-04-19
............\..........\........\........\...............\_primary.vhd,90,2017-04-19
............\..........\........\........\ram_ip
............\..........\........\........\......\verilog.prw,6779,2017-04-19
............\..........\........\........\......\verilog.psm,16968,2017-04-19
............\..........\........\........\......\_primary.dat,1978,2017-04-19
............\..........\........\........\......\_primary.dbs,1768,2017-04-19
............\..........\........\........\......\_primary.vhd,422,2017-04-19