FSK

代码说明：

  FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)

文件列表：

FSK
...\Code
...\....\DDS.v,908,2014-02-28
...\....\FSK.v,1047,2014-02-28
...\....\FSK_tb.v,345,2014-04-09
...\....\FSK_tb.v.bak,0,2014-04-09
...\....\Fs_Gen.v,832,2014-02-25
...\....\m.v,1433,2014-02-28
...\....\SIN14Bit.mif,206190,2014-02-27
...\....\SinRom.v,6231,2014-02-27
...\Modelsim
...\........\FSK.cr.mti,1763,2014-04-09
...\........\FSK.mpf,58213,2014-04-09
...\........\SIN14Bit.mif,206190,2014-02-27
...\........\SIN14Bit.ver,208624,2014-04-09
...\........\vsim.wlf,606208,2014-04-09
...\........\work
...\........\....\@d@d@s
...\........\....\......\verilog.asm,4864,2014-04-09
...\........\....\......\verilog.rw,1965,2014-04-09
...\........\....\......\_primary.dat,481,2014-04-09
...\........\....\......\_primary.dbs,820,2014-04-09
...\........\....\......\_primary.vhd,251,2014-04-09
...\........\....\@f@s@k
...\........\....\......\verilog.asm,9216,2014-04-09
...\........\....\......\verilog.rw,4348,2014-04-09
...\........\....\......\_primary.dat,906,2014-04-09
...\........\....\......\_primary.dbs,1120,2014-04-09
...\........\....\......\_primary.vhd,377,2014-04-09
...\........\....\@sin@rom
...\........\....\........\verilog.asm,13936,2014-04-09
...\........\....\........\verilog.rw,6856,2014-04-09
...\........\....\........\_primary.dat,1606,2014-04-09
...\........\....\........\_primary.dbs,665,2014-04-09
...\........\....\........\_primary.vhd,257,2014-04-09
...\........\....\fs_@gen
...\........\....\.......\verilog.asm,4480,2014-04-09
...\........\....\.......\verilog.rw,1750,2014-04-09
...\........\....\.......\_primary.dat,475,2014-04-09
...\........\....\.......\_primary.dbs,1006,2014-04-09
...\........\....\.......\_primary.vhd,280,2014-04-09
...\........\....\m_tb
...\........\....\....\verilog.asm,3904,2014-04-09
...\........\....\....\verilog.rw,1295,2014-04-09
...\........\....\....\_primary.dat,327,2014-04-09
...\........\....\....\_primary.dbs,493,2014-04-09
...\........\....\....\_primary.vhd,68,2014-04-09
...\........\....\wsj
...\........\....\...\verilog.asm,12792,2014-04-09
...\........\....\...\verilog.rw,2094,2014-04-09
...\........\....\...\_primary.dat,747,2014-04-09
...\........\....\...\_primary.dbs,1559,2014-04-09
...\........\....\...\_primary.vhd,310,2014-04-09
...\........\....\htm" target=_blank>_info,1799,2014-04-09
...\........\....\_temp
...\........\....\_vmake,26,2014-04-09