TLC1620

代码说明：

  基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)

文件列表：

TLC1620
.......\1650fa.pdf,491432,2015-04-23
.......\alterapll.v,16445,2015-04-23
.......\alterapll.v.bak,16793,2015-04-09
.......\DA_Serial_TIMING.v,4211,2015-04-23
.......\DA_Serial_TIMING.v.bak,4208,2015-04-23
.......\DA_TLC.cr.mti,259,2015-04-23
.......\DA_TLC.mpf,80154,2015-04-23
.......\TLC_tb.v,868,2015-04-23
.......\TLC_tb.v.bak,866,2015-04-23
.......\vsim.wlf,73728,2015-04-23
.......\work
.......\....\@d@a_@serial_@t@i@m@i@n@g
.......\....\.........................\verilog.asm64,27184,2015-04-23
.......\....\.........................\verilog.rw64,1061,2015-04-23
.......\....\.........................\_primary.dat,2625,2015-04-23
.......\....\.........................\_primary.dbs,3006,2015-04-23
.......\....\.........................\_primary.vhd,558,2015-04-23
.......\....\alterapll
.......\....\.........\verilog.asm64,54992,2015-04-23
.......\....\.........\verilog.rw64,2572,2015-04-23
.......\....\.........\_primary.dat,3741,2015-04-23
.......\....\.........\_primary.dbs,2320,2015-04-23
.......\....\.........\_primary.vhd,309,2015-04-23
.......\....\tb
.......\....\..\verilog.asm64,16960,2015-04-23
.......\....\..\verilog.rw64,723,2015-04-23
.......\....\..\_primary.dat,988,2015-04-23
.......\....\..\_primary.dbs,1422,2015-04-23
.......\....\..\_primary.vhd,64,2015-04-23
.......\....\htm" target=_blank>_info,1353,2015-04-23
.......\....\_temp
.......\....\.....\vlogbnd6he,2349,2015-04-23
.......\....\.....\vlogviqt68,3056,2015-04-23
.......\....\_vmake,26,2015-04-23