source

代码说明：

  altera DDR3 逻辑测试代码，这是工程实际调试好的代码，保证能用。(altera DDR3 vhdl code)

文件列表：

source
......\altera_avalon_half_rate_bridge.v,12996,2012-07-31
......\altera_avalon_half_rate_bridge_constraints.sdc,4054,2012-07-31
......\altmemphy-library
......\.................\auk_ddr3_hp_controller.ocp,488,2012-07-31
......\alt_ddrx_addr_cmd.v,14749,2012-07-31
......\alt_ddrx_afi_block.v,18475,2012-07-31
......\alt_ddrx_avalon_if.v,13358,2012-07-31
......\alt_ddrx_bank_timer.v,64882,2012-07-31
......\alt_ddrx_bank_timer_info.v,13927,2012-07-31
......\alt_ddrx_bank_timer_wrapper.v,122401,2012-07-31
......\alt_ddrx_bypass.v,45678,2012-07-31
......\alt_ddrx_cache.v,13668,2012-07-31
......\alt_ddrx_clock_and_reset.v,4262,2012-07-31
......\alt_ddrx_cmd_gen.v,22561,2012-07-31
......\alt_ddrx_cmd_queue.v,37685,2012-07-31
......\alt_ddrx_controller.v,76206,2012-07-31
......\alt_ddrx_csr.v,46438,2012-07-31
......\alt_ddrx_ddr2_odt_gen.v,11608,2012-07-31
......\alt_ddrx_ddr3_odt_gen.v,4915,2012-07-31
......\alt_ddrx_decoder.v,2454,2012-07-31
......\alt_ddrx_decoder_40.v,18708,2012-07-31
......\alt_ddrx_decoder_72.v,29831,2012-07-31
......\alt_ddrx_ecc.v,65689,2012-07-31
......\alt_ddrx_encoder.v,2057,2012-07-31
......\alt_ddrx_encoder_40.v,8560,2012-07-31
......\alt_ddrx_encoder_72.v,13197,2012-07-31
......\alt_ddrx_input_if.v,31325,2012-07-31
......\alt_ddrx_odt_gen.v,16806,2012-07-31
......\alt_ddrx_rank_monitor.v,45629,2012-07-31
......\alt_ddrx_state_machine.v,130403,2012-07-31
......\alt_ddrx_timing_param.v,71344,2012-07-31
......\alt_ddrx_wdata_fifo.v,7102,2012-07-31
......\alt_mem_phy_defines.v,5281,2012-07-31
......\ddr3.bsf,10112,2012-07-31
......\ddr3.ppf,15294,2012-07-31
......\ddr3.qip,4994,2012-07-31
......\ddr3.v,30213,2012-07-31
......\ddr3_advisor.ipa,54447,2012-07-31
......\ddr3_alt_ddrx_controller_wrapper.v,18045,2012-07-31
......\ddr3_bb.v,3473,2012-07-31
......\ddr3_controller_phy.v,15683,2012-07-31
......\ddr3_example_driver.v,31515,2012-07-31
......\ddr3_example_top.sdc,216,2012-07-31
......\ddr3_example_top.v,8176,2012-08-02
......\ddr3_example_top.v.bak,8149,2012-08-02
......\ddr3_ex_lfsr8.v,1393,2012-07-31
......\ddr3_high_performance_controller-library
......\........................................\auk_ddr3_hp_controller.ocp,488,2012-07-31
......\ddr3_phy.bsf,18415,2012-07-31
......\ddr3_phy.qip,2719,2012-07-31
......\ddr3_phy.v,33006,2012-07-31
......\ddr3_phy_alt_mem_phy.v,369493,2012-07-31
......\ddr3_phy_alt_mem_phy_pll.qip,311,2012-07-31
......\ddr3_phy_alt_mem_phy_pll.v,24560,2012-07-31
......\ddr3_phy_alt_mem_phy_pll.v_.bak,17808,2012-07-31
......\ddr3_phy_alt_mem_phy_pll_bb.v,19096,2012-07-31
......\ddr3_phy_alt_mem_phy_seq.vhd,1228613,2012-07-31
......\ddr3_phy_alt_mem_phy_seq_wrapper.v,20008,2012-07-31
......\ddr3_phy_bb.v,5141,2012-07-31
......\ddr3_phy_ddr_pins.tcl,62084,2012-07-31
......\ddr3_phy_ddr_timing.sdc,34355,2012-07-31
......\ddr3_phy_ddr_timing.tcl,5619,2012-07-31
......\ddr3_phy_report_timing.tcl,20637,2012-07-31
......\ddr3_phy_report_timing_core.tcl,84575,2012-07-31
......\ddr3_pin_assignments.tcl,17796,2012-07-31
......\greybox_tmp
......\...........\cbx_args.txt,2084,2012-07-31
......\testbench
......\.........\ddr3_example_top_tb.v,17314,2012-07-31
......\.........\ddr3_example_top_tb.v.tmp,17314,2012-07-31
......\.........\ddr3_full_mem_model.v,27450,2012-07-31
......\.........\ddr3_mem_model.v,27773,2012-07-31