Writing-Testbenches-using-System-Verilog

代码说明：

  writing testbench in system verilog

文件列表：

Writing Testbenches using System Verilog
........................................\1What is Verification.pdf,240970,2007-05-23
........................................\2Verification Technologies.pdf,438901,2007-05-23
........................................\3The Verification Plan.pdf,283664,2007-05-23
........................................\4High-Level Modeling.pdf,494854,2007-05-23
........................................\5Stimulus and Response.pdf,439322,2007-05-23
........................................\6Architecting Testbenches.pdf,344681,2007-05-23
........................................\7Simulation Management.pdf,293784,2007-05-23
........................................\back-matter.pdf,302320,2007-05-23
........................................\front-matter.pdf,211058,2007-05-23