32bit_multiply

代码说明：

  包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

文件列表：

multiply
........\bootcoder.v,472,2008-01-28
........\boot_mul.v,8631,2008-01-28
........\csa.v,211,2008-01-28
........\tb_bootmul.v,619,2008-01-28
........\tb_mul.v,663,2008-01-28
........\_42c_l.v,464,2008-01-28