Crazy_FPGA_Examples

代码说明：

  crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)

文件列表：

Crazy_FPGA_Examples
...................\01_Counter_Design
...................\.................\core
...................\.................\dev
...................\.................\...\Counter_Design.qpf,1281,2014-04-22
...................\.................\...\Counter_Design.qsf,3178,2014-05-19
...................\.................\...\Counter_Design.qws,2203,2014-05-19
...................\.................\...\output_files
...................\.................\...\............\Counter_Design.asm.rpt,7503,2014-04-22
...................\.................\...\............\Counter_Design.done,26,2014-05-19
...................\.................\...\............\Counter_Design.fit.rpt,125908,2014-04-22
...................\.................\...\............\Counter_Design.fit.smsg,703,2014-04-22
...................\.................\...\............\Counter_Design.fit.summary,624,2014-04-22
...................\.................\...\............\Counter_Design.flow.rpt,6762,2014-05-19
...................\.................\...\............\Counter_Design.jdi,233,2014-04-22
...................\.................\...\............\Counter_Design.map.rpt,21036,2014-05-19
...................\.................\...\............\Counter_Design.map.summary,477,2014-05-19
...................\.................\...\............\Counter_Design.pin,33017,2014-04-22
...................\.................\...\............\Counter_Design.sof,496867,2014-04-22
...................\.................\...\............\Counter_Design.sta.rpt,79720,2014-04-22
...................\.................\...\............\Counter_Design.sta.summary,934,2014-04-22
...................\.................\...\VIP_System.sdc,2393,2014-04-22
...................\.................\...\VIP_System.sdc.bak,2396,2014-04-10
...................\.................\doc
...................\.................\sim
...................\.................\...\Counter_Design_TB
...................\.................\...\.................\Counter_Design.v,1701,2013-10-21
...................\.................\...\.................\Counter_Design_TB.cr.mti,695,2014-07-03
...................\.................\...\.................\Counter_Design_TB.mpf,20229,2014-07-03
...................\.................\...\.................\Counter_Design_TB.v,2205,2013-10-24
...................\.................\...\.................\htm" target=_blank>transcript,210,2014-07-03
...................\.................\...\.................\vsim.wlf,73728,2014-04-10
...................\.................\...\.................\vsim_stacktrace.vstf,960,2013-10-21
...................\.................\...\.................\wave.do,1145,2013-10-21
...................\.................\...\.................\work
...................\.................\...\.................\....\@counter_@design
...................\.................\...\.................\....\................\verilog.prw,187,2014-04-10
...................\.................\...\.................\....\................\verilog.psm,3056,2014-04-10
...................\.................\...\.................\....\................\_primary.dat,377,2014-04-10
...................\.................\...\.................\....\................\_primary.dbs,424,2014-04-10
...................\.................\...\.................\....\................\_primary.vhd,252,2014-04-10
...................\.................\...\.................\....\@counter_@design_@t@b
...................\.................\...\.................\....\.....................\verilog.prw,526,2014-04-10
...................\.................\...\.................\....\.....................\verilog.psm,6752,2014-04-10
...................\.................\...\.................\....\.....................\_primary.dat,633,2014-04-10
...................\.................\...\.................\....\.....................\_primary.dbs,877,2014-04-10
...................\.................\...\.................\....\.....................\_primary.vhd,94,2014-04-10
...................\.................\...\.................\....\htm" target=_blank>_info,1347,2014-04-10
...................\.................\...\.................\....\_temp
...................\.................\...\.................\....\.....\vlog19ssna,395,2013-10-21
...................\.................\...\.................\....\.....\vlog2zrsty,395,2013-10-21
...................\.................\...\.................\....\.....\vlogik2gwb,396,2013-10-21
...................\.................\...\.................\....\_vmake,26,2014-04-10
...................\.................\src
...................\.................\...\Counter_Design.v,1710,2014-04-22
...................\.................\...\Counter_Design.v.bak,1710,2014-04-22
...................\02-1_LED_Display_Design_8BitAddr
...................\................................\core
...................\................................\dev
...................\................................\...\LED_Display_Design.qpf,1289,2013-10-27
...................\................................\...\LED_Display_Design.qsf,3863,2014-04-23
...................\................................\...\LED_Display_Design.qws,1756,2014-05-19
...................\................................\...\LED_Display_Design.tcl,3886,2014-04-23
...................\................................\...\output_files
...................\................................\...\............\LED_Display_Design.asm.rpt,9341,2014-04-23
...................\................................\...\............\LED_Display_Design.cdf,379,2014-05-18
...................\................................\...\............\LED_Display_Design.done,26,2014-04-23
...................\................................\...\............\LED_Display_Design.fit.rpt,140654,2014-04-23
...................\................................\...\............\LED_Display_Design.fit.smsg,703,2014-04-23
...................\................................\...\............\LED_Display_Design.fit.summary,637,2014-04-23
...................\................................\...\............\LED_Display_Design.flow.rpt,7671,2014-04-23
...................\................................\...\............\LED_Display_Design.jdi,237,2014-04-23
...................\................................\...\............\LED_Display_Design.map.rpt,23108,2014-04-23
...................\................................\...\............\LED_Display_Design.map.smsg,160,2014-04-10
...................\................................\...\............\LED_Display_Design.map.summary,490,2014-04-23
...................\................................\...\............\LED_Display_Design.pin,32998,2014-04-23
...................\................................\...\............\LED_Display_Design.pof,524494,2014-04-23
...................\................................\...\............\LED_Display_Design.pti_db_list.ddb,217,2013-10-27
...................\................................\...\............\LED_Display_Design.sof,496875,2014-04-23
...................\................................\...\............\LED_Display_Design.sta.rpt,227864,2014-04-23
...................\................................\...\............\LED_Display_Design.sta.summary,934,2014-04-23
...................\................................\...\............\LED_Display_Design.tis_db_list.ddb,217,2013-10-27
...................\................................\...\............\output_file.jic,524511,2014-04-22
...................\................................\...\............\output_file.map,189,2013-10-27
...................\................................\...\VIP_System.sdc,2393,2014-04-22
...................\................................\...\VIP_System.sdc.bak,2394,2013-10-23
...................\................................\doc
...................\................................\sim
...................\................................\...\LED_Display_TB
...................\................................\...\..............\led_addr_display.v,2703,2013-10-27
...................\................................\...\..............\LED_Display_TB.cr.mti,739,2014-07-03
...................\................................\...\..............\LED_Display_TB.mpf,20254,2014-07-03
...................\................................\...\..............\LED_Display_TB.v,2299,2014-07-03
...................\................................\...\..............\vsim.wlf,98304,2014-07-03
...................\................................\...\..............\wave.do,1764,2014-07-03
...................\................................\...\..............\work
...................\................................\...\..............\....\@l@e@d_@display_@t@b
...................\................................\...\..............\....\....................\verilog.prw,518,2014-07-03
...................\................................\...\..............\....\....................\verilog.psm,7000,2014-07-03
...................\................................\...\..............\....\....................\_primary.dat,668,2014-07-03