RS

代码说明：

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

文件列表：

RS(204,188)译码器的设计
.......................\BM_KES.v,5102,2006-07-02
.......................\CheinSearch.v,3006,2006-07-07
.......................\ff_mul.v,5001,2006-07-02
.......................\forney.v,9387,2006-07-07
.......................\ROM_INV.mif,3452,2006-07-02
.......................\rom_inv.v,5824,2006-07-02
.......................\rom_power.mif,3447,2006-07-06
.......................\rom_power.v,5846,2006-07-06
.......................\RS(204,188)译码器说明.txt,450,2006-07-07
.......................\rs_decoder.v,1940,2006-07-07
.......................\SyndromeCalc.v,2694,2006-07-06
RS编码器
........\mula_0.v,196,2009-07-20
........\mula_1.v,205,2009-07-20
........\mula_10.v,248,2009-07-20
........\mula_11.v,255,2009-07-20
........\mula_12.v,255,2009-07-20
........\mula_13.v,269,2009-07-21
........\mula_14.v,283,2009-07-21
........\mula_15.v,297,2009-07-20
........\mula_16.v,321,2009-07-21
........\mula_17.v,328,2009-07-21
........\mula_18.v,325,2009-07-20
........\mula_2.v,212,2009-07-21
........\mula_21.v,288,2009-07-21
........\mula_22.v,277,2009-07-20
........\mula_25.v,281,2009-07-20
........\mula_3.v,219,2009-07-21
........\mula_31.v,260,2009-07-20
........\mula_32.v,261,2009-07-20
........\mula_35.v,309,2009-07-20
........\mula_38.v,337,2009-07-20
........\mula_4.v,226,2009-07-21
........\mula_45.v,289,2009-07-21
........\mula_48.v,293,2009-07-20
........\mula_5.v,233,2009-07-20
........\mula_51.v,322,2009-07-21
........\mula_59.v,269,2009-07-20
........\mula_6.v,247,2009-07-20
........\mula_61.v,220,2009-07-20
........\mula_7.v,248,2009-07-20
........\mula_8.v,247,2009-07-20
........\mula_9.v,247,2009-07-20
........\mul_encode.vhd,3216,2008-01-21
........\rscode.v,2256,2009-07-21
........\rscode.vhd,7911,2007-12-11
........\rscode.vwf,8616,2009-07-21
........\rstestbench.vhd,1142,2008-05-05
........\testbenchmul.vhd,1245,2007-12-08
........\testbenchmul_encode.vhd,1273,2008-01-21