▍1. lcd_1206
Verilog控制lcd1206显示源程序(Verilog control lcd1206 display source program)
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▍5. new
1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。 4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)
▍6. 基于FPGA和IP核的FIR低通滤波器
用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
▍7. code
Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage.
▍8. 基于XILINX FPGA的OFDM通信系统基带设计
基于XILINX FPGA的OFDM通信系统基带设计 浙江大学出版社出版 ofdm verilog HDL语言(Baseband Design of OFDM communication system based on XILINX FPGA, published by Zhejiang University press)
▍10. FPGA-CNN-master
fpga硬件实现cnn代码，学习可用。了解基本的深度学习概念和实现方法(FPGA hardware implementation of the code, used for learning)
▍11. FPGA_SOURCE_CODE
ad9910 FPGA VERILOG 初始化代码，(Ad9910 FPGA VERILOG initialization code)
▍12. freq_100M
用于检测100MHZ频率，带51单片机软核，控制外部液晶显示器以及按键等(Used to detect 100MHZ frequency, with 51 SCM soft core, control of external LCD monitors and buttons, etc.)
▍13. ahb2apb
ARM m4 FPGA开发模块，用于 ahb2apb的模块接口(ARM M4 FPGA development module for ahb2apb module interface)
▍14. 无线通信的MATLAB和FPGA实现
无线通信的MATLAB和FPGA实现，书籍，经典无线通信，代码可以实现(Wireless communication MATLAB and FPGA implementation, books, classic wireless communications, code can be achieved)
▍15. fft1024 verilog代码
fft1024 verilog 代码 可以编译成功 建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)
▍17. SPWM信号产生系统IP软核设计及验证
针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full digital three-phase SPWM signal generation system. The power frequency of IP core is the auxiliary control is implemented through digital frequency synthesis technology. The power frequency accuracy of 16. By adjusting the control parameters, 7 and 8 levels of power frequency and carrier frequency are realized respectively. Finally, the control of the power frequency and carrier frequency is realized. A test system based on FPGA is built, which verifies the correctness of the system function)
▍18. 2静电场-无电轴法
美国工程电磁场，电磁场分析与学习American Engineering Electromagnetic Field(American Engineering Electromagnetic Field)
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