▍1. MUX21A
说明: 基于vivado实现的具有数据选择器功能的ip(base on vivado mux2_to_1)
说明: 基于vivado实现的具有数据选择器功能的ip(base on vivado mux2_to_1)
AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
说明: AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
实现最高速率为6.6Gbps的数据传输,有高速串并转换功能,适合高速率的场景。(Achieve the highest rate of 6.6Gbps data transmission, high-speed serial and parallel conversion function, suitable for high-speed scenarios.)
此文档详细说明了如何利用Modelsim软件对FPGA逻辑代码进行功能仿真和时序仿真的方法,并通过相关例子进行讲解说明(This document explains in detail how to use Modelsim software to perform functional simulation and time series simulation of FPGA logic code, and explain how to use some examples.)
通过LED闪烁控制器的代码,使用Vivado工具配置定义一个IP核,在用户工程中可随意添加这个IP核作为设计的一部分,如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
Verilog写的led灯,可用Vivado/ISE仿真平台仿真(Progress is not created by contented people.)
说明: 使用Verilog HDL ,FM调制信号。(Using Verilog, HDL, and FM modulation signals.)
vivado的入门教程,从工程创建到简单的系统搭建,以及sim仿真,都详细的以图片的形式给出,适合初学者(Vivado tutorial, from engineering creation to simple system building, and sim simulation, are detailed in the form of pictures given, suitable for beginners)
GTP IP核,高速通信必须学习的部分。(GTP IP kernel, part of high-speed communication that must be learned.)