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8_1
一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
- 2020-12-17 08:29:12下载
- 积分：1
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verilog
基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)
- 2011-12-01 20:19:48下载
- 积分：1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分：1
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soft for changing Verilog code to c++ code ,c code
将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code
- 2022-01-24 14:30:24下载
- 积分：1
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直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为...
直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
- 2022-06-17 05:09:27下载
- 积分：1
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Kluwer.Academic.The.Verilog.Hardware.Description
Kluwer academic the verilog hardware description language fith edition
- 2014-10-08 08:11:42下载
- 积分：1
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vhdl+verilog
小波提升算法源码，里面一个txt文件可以当作算法参考；(Wavelet lifting algorithm source code, inside a TXT file can be used as algorithm reference;)
- 2018-06-20 09:28:28下载
- 积分：1
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5
fpga paper function fff(fpga paper function)
- 2010-03-11 23:15:24下载
- 积分：1
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vhdl 基于ADC0809 A/D转换控制器的设计实验
vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809
- 2022-02-25 21:38:23下载
- 积分：1
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用VHDL编写的计算器，能实现简单的加减乘除四则运算
用VHDL编写的计算器，能实现简单的加减乘除四则运算
- 2022-03-18 17:26:25下载
- 积分：1
