-
802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分：1
-
math_real
in this code very useful for designing real number concept
- 2013-11-19 19:54:40下载
- 积分：1
-
de2 vga controller board can also be used for other development
de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development
- 2022-05-17 01:30:37下载
- 积分：1
-
用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制....
用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
- 2022-12-17 02:20:02下载
- 积分：1
-
vhdl
vhdl code for internet interface
- 2014-12-04 04:58:04下载
- 积分：1
-
AD9250 204b Verilog源码
说明： AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分：1
-
使用 fpga 斯巴达在 xilinx 的 SD 卡
它工作斯巴达。
使用 xilinx ise
在斯巴达 6e
效果很好
- 2023-08-23 20:20:04下载
- 积分：1
-
stm8uart
Demo program for use UART STM8S
- 2013-09-05 03:18:35下载
- 积分：1
-
TIMING LEARNING
TIMING LEARNING -TIMING LEARNING
- 2023-04-26 09:15:03下载
- 积分：1
-
FMCOS
复旦cpu COS
- 2015-12-23 15:53:42下载
- 积分：1
