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VHDL language used to achieve 8
用VHDL语言实现8-3线编码器，16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder
- 2023-08-20 10:35:02下载
- 积分：1
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In this case is a convolutional code on a simple algorithm, using verilog HDL la...
本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.
- 2022-02-05 20:03:55下载
- 积分：1
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vote7
说明： 自己设计的一个其人投票系统，对于VHDL初学者可以参考下(One of their own design their human voting system, for VHDL beginners can refer to the following)
- 2009-08-30 09:25:04下载
- 积分：1
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vhdl交通灯实验报告
vhdl交通灯实验报告-VHDL traffic lights Experimental Report
- 2022-02-13 04:55:13下载
- 积分：1
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Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.
- 2022-12-08 19:40:03下载
- 积分：1
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CPUver2
这是一个有关单周期CPU设计的一个参考，里面顶层模块已经写好，而其他模块的内容则是以注释的形式存在，如果要跑这个代码的话，把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。(
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这是一个有关单周期CPU设计的一个参考，里面顶层模块已经写好，而其他模块的内容则是以注释的形式存在，如果要跑这个代码的话，把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。
This is a reference about a single cycle CPU design, top-level module which has been written, and the contents of the other modules exist in the form of comments, if run this code, those codes include the commented out and then each module is uncommented to commented code.)
- 2016-05-15 15:59:07下载
- 积分：1
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ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户
ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
- 2022-02-25 00:06:16下载
- 积分：1
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用vlog语言编制程序CPU控制器源代码…
用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
- 2022-02-15 12:37:59下载
- 积分：1
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tdm_latest[1]
TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)
- 2010-07-07 15:28:06下载
- 积分：1
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this project is based on half adder ,full adder,half subtractor and full subtrac...
this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
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this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
- 2022-12-30 21:40:03下载
- 积分：1
